/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ |
D | psoc_global_conf_masks.h | 23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF 27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF 39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF [all …]
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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D | dra72x-mmc-iodelay.dtsi | 45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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D | imx35-pinfunc.h | 13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 [all …]
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D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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D | imx53-cx9020.dts | 20 reg = <0x70000000 0x20000000>, 21 <0xb0000000 0x20000000>; 24 display-0 { 26 #size-cells = <0>; 30 pinctrl-0 = <&pinctrl_ipu_disp0>; 32 port@0 { 33 reg = <0>; 66 #size-cells = <0>; 68 port@0 { 69 reg = <0>; [all …]
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/kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
D | clk-hi3620.c | 67 { HI3620_OSC32K, "osc32k", NULL, 0, 32768, }, 68 { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, }, 69 { HI3620_PCLK, "pclk", NULL, 0, 26000000, }, 70 { HI3620_PLL_ARM0, "armpll0", NULL, 0, 1600000000, }, 71 { HI3620_PLL_ARM1, "armpll1", NULL, 0, 1600000000, }, 72 { HI3620_PLL_PERI, "armpll2", NULL, 0, 1440000000, }, 73 { HI3620_PLL_USB, "armpll3", NULL, 0, 1440000000, }, 74 { HI3620_PLL_HDMI, "armpll4", NULL, 0, 1188000000, }, 75 { HI3620_PLL_GPU, "armpll5", NULL, 0, 1300000000, }, 80 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, }, [all …]
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/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/kernel/linux/linux-5.10/sound/soc/meson/ |
D | aiu.h | 18 PCLK = 0, 63 #define AIU_IEC958_BPF 0x000 64 #define AIU_958_MISC 0x010 65 #define AIU_IEC958_DCU_FF_CTRL 0x01c 66 #define AIU_958_CHSTAT_L0 0x020 67 #define AIU_958_CHSTAT_L1 0x024 68 #define AIU_958_CTRL 0x028 69 #define AIU_I2S_SOURCE_DESC 0x034 70 #define AIU_I2S_DAC_CFG 0x040 71 #define AIU_I2S_SYNC 0x044 [all …]
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/kernel/linux/linux-5.10/arch/sh/drivers/pci/ |
D | pci-sh7780.h | 13 #define PCIECR 0xFE000008 14 #define PCIECR_ENBL 0x01 17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 25 #define SH7780_PCIAIR 0x11C /* Error Address Register */ 26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */ 27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ [all …]
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/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt7601u/ |
D | eeprom.h | 12 #define MT7601U_EE_MAX_VER 0x0d 18 MT_EE_CHIP_ID = 0x00, 19 MT_EE_VERSION_FAE = 0x02, 20 MT_EE_VERSION_EE = 0x03, 21 MT_EE_MAC_ADDR = 0x04, 22 MT_EE_NIC_CONF_0 = 0x34, 23 MT_EE_NIC_CONF_1 = 0x36, 24 MT_EE_COUNTRY_REGION = 0x39, 25 MT_EE_FREQ_OFFSET = 0x3a, 26 MT_EE_NIC_CONF_2 = 0x42, [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/kernel/linux/linux-5.10/drivers/pinctrl/ |
D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/kernel/linux/linux-5.10/drivers/thermal/ti-soc-thermal/ |
D | omap5xxx-bandgap.h | 29 #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0 30 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150 31 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8 32 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4 33 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8 34 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC 37 #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4 38 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C 39 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4 40 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0 [all …]
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D | dra752-bandgap.h | 27 * DRA752_BANDGAP_BASE 0x4a0021e0 34 #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 35 #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 36 #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c 37 #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 40 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 41 #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 42 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 43 #define DRA752_DTEMP_CORE_1_OFFSET 0x20c 44 #define DRA752_DTEMP_CORE_2_OFFSET 0x210 [all …]
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/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/ |
D | mt76x02_eeprom.h | 13 MT_EE_CHIP_ID = 0x000, 14 MT_EE_VERSION = 0x002, 15 MT_EE_MAC_ADDR = 0x004, 16 MT_EE_PCI_ID = 0x00A, 17 MT_EE_ANTENNA = 0x022, 18 MT_EE_CFG1_INIT = 0x024, 19 MT_EE_NIC_CONF_0 = 0x034, 20 MT_EE_NIC_CONF_1 = 0x036, 21 MT_EE_COUNTRY_REGION_5GHZ = 0x038, 22 MT_EE_COUNTRY_REGION_2GHZ = 0x039, [all …]
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/kernel/linux/linux-5.10/drivers/pci/controller/ |
D | pcie-iproc.c | 30 #define RC_PCIE_RST_OUTPUT_SHIFT 0 32 #define PAXC_RESET_MASK 0x7f 34 #define GIC_V3_CFG_SHIFT 0 37 #define MSI_ENABLE_CFG_SHIFT 0 40 #define CFG_IND_ADDR_MASK 0x00001ffc 43 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 45 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 47 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 49 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc 50 #define CFG_ADDR_CFG_TYPE_SHIFT 0 [all …]
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/kernel/linux/linux-5.10/block/partitions/ |
D | acorn.c | 34 dr = (struct adfs_discrecord *)(data + 0x1c0); in adfs_partition() 36 if (dr->disc_size == 0 && dr->disc_size_high == 0) in adfs_partition() 63 #define RISCIX_MAGIC cpu_to_le32(0x4a657320) 91 for (part = 0; part < 8; part++) { in riscix_partition() 93 memcmp(rr->part[part].name, "All\0", 4)) { in riscix_partition() 114 #define LINUX_NATIVE_MAGIC 0xdeafa1de 115 #define LINUX_SWAP_MAGIC 0xdeafab1e 161 unsigned long first_sector = 0; in adfspart_check_CUMANA() 162 unsigned int start_blk = 0; in adfspart_check_CUMANA() 199 nr_sects = (data[0x1fd] + (data[0x1fe] << 8)) * in adfspart_check_CUMANA() [all …]
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/kernel/linux/linux-5.10/drivers/thermal/tegra/ |
D | tegra132-soctherm.c | 23 #define TEGRA132_THERMTRIP_ANY_EN_MASK (0x1 << 28) 24 #define TEGRA132_THERMTRIP_MEM_EN_MASK (0x1 << 27) 25 #define TEGRA132_THERMTRIP_GPU_EN_MASK (0x1 << 26) 26 #define TEGRA132_THERMTRIP_CPU_EN_MASK (0x1 << 25) 27 #define TEGRA132_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) 28 #define TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) 29 #define TEGRA132_THERMTRIP_CPU_THRESH_MASK (0xff << 8) 30 #define TEGRA132_THERMTRIP_TSENSE_THRESH_MASK 0xff 32 #define TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) 33 #define TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) [all …]
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D | tegra124-soctherm.c | 23 #define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28) 24 #define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27) 25 #define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26) 26 #define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25) 27 #define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) 28 #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) 29 #define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8) 30 #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff 32 #define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) 33 #define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) [all …]
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