/kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
D | stv090x_reg.h | 13 #define STV090x_MID 0xf100 16 #define STV090x_OFFST_MRELEASE_FIELD 0 19 #define STV090x_DACR1 0xf113 22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0 25 #define STV090x_DACR2 0xf114 26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0 29 #define STV090x_OUTCFG 0xf11c 39 #define STV090x_MODECFG 0xf11d 41 #define STV090x_IRQSTATUS3 0xf120 52 #define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0 [all …]
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/kernel/linux/linux-5.10/drivers/media/pci/cx25821/ |
D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() 25 u32 tmp = 0; in medusa_enable_bluefield_output() 63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output() 64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output() 69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output() 70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output() 72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output() [all …]
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/kernel/linux/linux-5.10/drivers/clk/pistachio/ |
D | clk-pistachio.c | 19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0), 20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1), 21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2), 22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3), 23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4), 24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5), 25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6), 26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7), 27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8), 28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9), [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
D | qcom,qmp-usb3-dp-phy.yaml | 81 "^usb3-phy@[0-9a-f]+$": 109 const: 0 112 const: 0 121 "^dp-phy@[0-9a-f]+$": 139 const: 0 167 reg = <0x088e9000 0x18c>, 168 <0x088e8000 0x10>, 169 <0x088ea000 0x40>; 174 ranges = <0x0 0x088e9000 0x2000>; 190 reg = <0x200 0x128>, [all …]
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | sam9x60.dtsi | 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 47 reg = <0x20000000 0x10000000>; 53 #clock-cells = <0>; 58 #clock-cells = <0>; 64 reg = <0x00300000 0x100000>; 67 ranges = <0 0x00300000 0x100000>; 78 #size-cells = <0>; 80 reg = <0x00500000 0x100000 [all …]
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D | sama5d2.dtsi | 28 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 45 reg = <0x740000 0x1000>; 61 reg = <0x73C000 0x1000>; 77 reg = <0x20000000 0x20000000>; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 89 #clock-cells = <0>; [all …]
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D | at91sam9263.dtsi | 39 #size-cells = <0>; 41 cpu@0 { 44 reg = <0>; 50 reg = <0x20000000 0x08000000>; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 69 reg = <0x00300000 0x14000>; 72 ranges = <0 0x00300000 0x14000>; [all …]
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D | at91sam9260.dtsi | 40 #size-cells = <0>; 42 cpu@0 { 45 reg = <0>; 51 reg = <0x20000000 0x04000000>; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 69 #clock-cells = <0>; 76 reg = <0x002ff000 0x2000>; [all …]
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D | at91sam9261.dtsi | 37 #size-cells = <0>; 39 cpu@0 { 42 reg = <0>; 48 reg = <0x20000000 0x08000000>; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 67 reg = <0x00300000 0x28000>; 70 ranges = <0 0x00300000 0x28000>; [all …]
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D | at91sam9rl.dtsi | 42 #size-cells = <0>; 44 cpu@0 { 47 reg = <0>; 53 reg = <0x20000000 0x04000000>; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 71 #clock-cells = <0>; 78 reg = <0x00300000 0x10000>; [all …]
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D | at91sam9x5.dtsi | 43 #size-cells = <0>; 45 cpu@0 { 48 reg = <0>; 54 reg = <0x20000000 0x10000000>; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 66 #clock-cells = <0>; 67 clock-frequency = <0>; 72 #clock-cells = <0>; 79 reg = <0x00300000 0x8000>; [all …]
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D | at91sam9g45.dtsi | 45 #size-cells = <0>; 47 cpu@0 { 50 reg = <0>; 56 reg = <0x70000000 0x10000000>; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 68 #clock-cells = <0>; 69 clock-frequency = <0>; 74 #clock-cells = <0>; 81 reg = <0x00300000 0x10000>; [all …]
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/kernel/linux/linux-5.10/drivers/memory/tegra/ |
D | tegra124.c | 15 .id = 0x00, 19 .id = 0x01, 23 .reg = 0x228, 27 .reg = 0x2e8, 28 .shift = 0, 29 .mask = 0xff, 30 .def = 0xc2, 33 .id = 0x02, 37 .reg = 0x228, 41 .reg = 0x2f4, [all …]
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D | tegra30.c | 36 .id = 0x00, 40 .id = 0x01, 44 .reg = 0x228, 48 .reg = 0x2e8, 49 .shift = 0, 50 .mask = 0xff, 51 .def = 0x4e, 54 .id = 0x02, 58 .reg = 0x228, 62 .reg = 0x2f4, [all …]
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D | tegra210.c | 12 .id = 0x00, 16 .id = 0x01, 20 .reg = 0x228, 24 .reg = 0x2e8, 25 .shift = 0, 26 .mask = 0xff, 27 .def = 0xc2, 30 .id = 0x02, 34 .reg = 0x228, 38 .reg = 0x2f4, [all …]
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D | tegra114.c | 15 .id = 0x00, 19 .id = 0x01, 23 .reg = 0x228, 27 .reg = 0x2e8, 28 .shift = 0, 29 .mask = 0xff, 30 .def = 0x4e, 33 .id = 0x02, 37 .reg = 0x228, 41 .reg = 0x2f4, [all …]
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/kernel/linux/linux-5.10/drivers/soc/renesas/ |
D | r8a774a1-sysc.c | 17 { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU, 24 { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON, 26 { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU, 28 { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU, 30 { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU, 32 { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU, 34 { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON }, [all …]
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D | r8a774e1-sysc.c | 17 { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 19 { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 20 { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 21 { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 22 { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 23 { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 24 { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 25 { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 26 { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, [all …]
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D | r8a7796-sysc.c | 17 { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU, 24 { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON, 26 { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU, 28 { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU, 30 { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU, 32 { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU, 34 { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON }, [all …]
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D | r8a77980-sysc.c | 17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON, 20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, 22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, 24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, 26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, 28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON }, 29 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON }, 30 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR }, 31 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR }, [all …]
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D | r8a7795-sysc.c | 17 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU, 24 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU, 26 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU, 28 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON, 30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU, 32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU, 34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU, [all …]
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/kernel/linux/linux-5.10/drivers/nvmem/ |
D | sunxi_sid.c | 21 #define SUN8I_SID_PRCTL 0x40 22 #define SUN8I_SID_RDKEY 0x60 24 #define SUN8I_SID_OFFSET_MASK 0x1FF 26 #define SUN8I_SID_OP_LOCK (0xAC << 8) 47 return 0; in sunxi_sid_read() 71 writel(0, sid->base + SUN8I_SID_PRCTL); in sun8i_sid_register_readout() 73 return 0; in sun8i_sid_register_readout() 77 * On Allwinner H3, the value on the 0x200 offset of the SID controller seems 100 return 0; in sun8i_sid_read_by_reg() 109 return 0; in sun8i_sid_read_by_reg() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_4_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]
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/kernel/linux/linux-5.10/drivers/clk/uniphier/ |
D | clk-uniphier-mio.c | 38 .reg = 0x30 + 0x200 * (ch), \ 40 0x00031000, \ 41 0x00031000, \ 42 0x00031000, \ 43 0x00031000, \ 44 0x00001300, \ 45 0x00001300, \ 46 0x00001300, \ 47 0x00001300, \ 50 0x00000000, \ [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
D | oss_3_0_1_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff 28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 29 #define IH_VMID_1_LUT__PASID_MASK 0xffff 30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_2_LUT__PASID_MASK 0xffff 32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_3_LUT__PASID_MASK 0xffff 34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 35 #define IH_VMID_4_LUT__PASID_MASK 0xffff 36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 [all …]
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