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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dti,am654-hbmc.txt23 reg = <0x0 0x47000000 0x0 0x100>;
31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
37 reg = <0x0 0x47034000 0x0 0x100>,
38 <0x5 0x00000000 0x1 0x0000000>;
42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
44 mux-controls = <&hbmc_mux 0>;
47 flash@0,0 {
49 reg = <0x0 0x0 0x4000000>;
Dqcom_nandc.txt35 - #size-cells: <0>
45 number (e.g., 0, 1, 2, etc.)
63 reg = <0x1ac00000 0x800>;
75 #size-cells = <0>;
77 nand@0 {
78 reg = <0>;
88 partition@0 {
90 reg = <0 0x58a0000>;
95 reg = <0x58a0000 0x4000000>;
103 reg = <0x79b0000 0x1000>;
[all …]
Dcypress,hyperflash.txt10 flash@0 {
12 reg = <0x0 0x4000000>;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/compressed/
Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
36 int status, i = 0x4000000; in icedcc_putc()
39 if (--i < 0) in icedcc_putc()
42 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
45 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
53 int status, i = 0x4000000; in icedcc_putc()
56 if (--i < 0) in icedcc_putc()
59 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
62 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
69 int status, i = 0x4000000; in icedcc_putc()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
34 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
38 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
39 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-5.10/arch/arm/configs/
Dtrizeps4_defconfig77 CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
82 CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atlx/
Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmstar-infinity3-msc313e.dtsi12 reg = <0x20000000 0x4000000>;
Dmstar-infinity-msc313.dtsi12 reg = <0x20000000 0x4000000>;
Dmstar-mercury5-ssc8336n.dtsi12 reg = <0x20000000 0x4000000>;
Dkirkwood-lschlv2.dts12 reg = <0x00000000 0x4000000>;
Dusb_a9g20_common.dtsi18 reg = <0x20000000 0x4000000>;
21 i2c-gpio-0 {
24 reg = <0x56>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reserved-memory/
Dreserved-memory.txt98 reg = <0x40000000 0x40000000>;
110 size = <0x4000000>;
111 alignment = <0x2000>;
116 reg = <0x78000000 0x800000>;
121 reg = <0x77000000 0x4000000>;
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/
Dgoya.h11 #define SRAM_CFG_BAR_ID 0
15 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
16 #define MSIX_BAR_SIZE 0x1000ull /* 4KB */
18 #define CFG_BASE 0x7FFC000000ull
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
21 #define SRAM_BASE_ADDR 0x7FF0000000ull
22 #define SRAM_SIZE 0x32A0000 /* 50.625MB */
24 #define DRAM_PHYS_BASE 0x0ull
26 #define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
27 #define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/
Dciu2.txt13 the CIU and may have a value between 0 and 63. The second cell is
14 the bit within the bank and may also have a value between 0 and 63.
21 * 1) Controller register (0..63)
22 * 2) Bit within the register (0..63)
24 #address-cells = <0>;
26 reg = <0x10701 0x00000000 0x0 0x4000000>;

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