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/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dreg_aic.h20 #define AR_SM_BASE 0xa200
21 #define AR_SM1_BASE 0xb200
22 #define AR_AGC_BASE 0x9e00
24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mp-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x228 0x488 0x5F0 0x0 0x6 0x49>,
77 <0x228 0x488 0x000 0x0 0x0 0x49>;
/kernel/linux/linux-5.10/drivers/media/usb/stk1160/
Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_util.c15 #define QSEED3_HW_VERSION 0x00
16 #define QSEED3_OP_MODE 0x04
17 #define QSEED3_RGB2Y_COEFF 0x08
18 #define QSEED3_PHASE_INIT 0x0C
19 #define QSEED3_PHASE_STEP_Y_H 0x10
20 #define QSEED3_PHASE_STEP_Y_V 0x14
21 #define QSEED3_PHASE_STEP_UV_H 0x18
22 #define QSEED3_PHASE_STEP_UV_V 0x1C
23 #define QSEED3_PRELOAD 0x20
24 #define QSEED3_DE_SHARPEN 0x24
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/freescale/fs_enet/
Dmac-scc.c95 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); in do_pd_setup()
99 fep->scc.sccp = of_iomap(ofdev->dev.of_node, 0); in do_pd_setup()
109 return 0; in do_pd_setup()
122 fep->scc.hthi = 0; in setup_data()
123 fep->scc.htlo = 0; in setup_data()
129 return 0; in setup_data()
145 return 0; in allocate_bd()
174 W16(ep, sen_gaddr1, 0); in set_multicast_start()
175 W16(ep, sen_gaddr2, 0); in set_multicast_start()
176 W16(ep, sen_gaddr3, 0); in set_multicast_start()
[all …]
/kernel/linux/linux-5.10/drivers/iommu/
Dmtk_iommu_v1.c37 #define REG_MMU_PT_BASE_ADDR 0x000
39 #define F_ALL_INVLD 0x2
40 #define F_MMU_INV_RANGE 0x1
41 #define F_INVLD_EN0 BIT(0)
44 #define F_MMU_FAULT_VA_MSK 0xfffff000
47 #define REG_MMU_CTRL_REG 0x210
49 #define REG_MMU_IVRP_PADDR 0x214
50 #define REG_MMU_INT_CONTROL 0x220
51 #define F_INT_TRANSLATION_FAULT BIT(0)
60 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
[all …]
Dtegra186.c45 for (i = 0; i < mc->soc->num_clients; i++) { in tegra186_mc_program_sid()
73 .override = 0x000,
74 .security = 0x004,
80 .override = 0x070,
81 .security = 0x074,
87 .override = 0x0a8,
88 .security = 0x0ac,
94 .override = 0x0b0,
95 .security = 0x0b4,
101 .override = 0x0e0,
[all …]
/kernel/linux/linux-5.10/sound/soc/bcm/
Dcygnus-pcm.c30 #define INTH_R5F_STATUS_OFFSET 0x040
31 #define INTH_R5F_CLEAR_OFFSET 0x048
32 #define INTH_R5F_MASK_SET_OFFSET 0x050
33 #define INTH_R5F_MASK_CLEAR_OFFSET 0x054
35 #define BF_REARM_FREE_MARK_OFFSET 0x344
36 #define BF_REARM_FULL_MARK_OFFSET 0x348
40 #define SRC_RBUF_0_RDADDR_OFFSET 0x500
41 #define SRC_RBUF_1_RDADDR_OFFSET 0x518
42 #define SRC_RBUF_2_RDADDR_OFFSET 0x530
43 #define SRC_RBUF_3_RDADDR_OFFSET 0x548
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
Dr8169_main.c66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75 #define OCP_STD_PHY_BASE 0xa400
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8162) },
161 { PCI_VDEVICE(REALTEK, 0x8167) },
162 { PCI_VDEVICE(REALTEK, 0x8168) },
[all …]
/kernel/linux/patches/linux-5.10/hispark_taurus_patch/
Dhispark_taurus.patch47 index 0b3cd7a33..763d37e86 100644
118 @@ -0,0 +1,270 @@
148 + reg = <0x82000000 0x20000000>;
233 + spidev@0 {
235 + reg = <0>;
236 + pl022,interface = <0>;
237 + pl022,com-mode = <0>;
245 + spidev@0 {
247 + reg = <0>;
248 + pl022,interface = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/qed/
Dqed_debug.c90 return ((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]); in cond5()
95 return ((r[0] >> imm[0]) & imm[1]) != imm[2]; in cond7()
100 return (r[0] & imm[0]) != imm[1]; in cond6()
105 return ((r[0] & imm[0]) >> imm[1]) != in cond9()
106 (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5])); in cond9()
111 return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]); in cond10()
116 return (r[0] & ~imm[0]) != imm[1]; in cond4()
121 return (r[0] & ~r[1]) != imm[0]; in cond0()
126 return r[0] != imm[0]; in cond1()
131 return r[0] != r[1] && r[2] == imm[0]; in cond11()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/
Dt4_regs.h38 #define MYPF_BASE 0x1b000
41 #define PF0_BASE 0x1e000
44 #define PF_STRIDE 0x400
51 #define MYPORT_BASE 0x1c000
54 #define PORT0_BASE 0x20000
57 #define PORT_STRIDE 0x2000
74 #define SGE_PF_KDOORBELL_A 0x0
83 #define PIDX_S 0
86 #define SGE_VF_KDOORBELL_A 0x0
92 #define PIDX_T5_S 0
[all …]
/kernel/linux/patches/linux-4.19/hispark_taurus_patch/
Dhispark_taurus.patch2 index 1877da816..0b45060b7 100644
188 @@ -0,0 +1,240 @@
218 + #size-cells = <0>;
220 + cpu@0 {
223 + reg = <0>;
261 + opp-freq = <0 1 2 3 4>;
271 + reg = <0x80000000 0x40000000>;
309 + spidev@0 {
311 + reg = <0>;
312 + pl022,interface = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra210.c33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
43 #define PLLC_OUT 0x84
[all …]
/kernel/linux/linux-5.10/Documentation/trace/
Dhistogram.rst216 field:unsigned short common_type; offset:0; size:2; signed:0;
217 field:unsigned char common_flags; offset:2; size:1; signed:0;
218 field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
221 field:unsigned long call_site; offset:8; size:8; signed:0;
222 field:const void * ptr; offset:16; size:8; signed:0;
223 field:size_t bytes_req; offset:24; size:8; signed:0;
224 field:size_t bytes_alloc; offset:32; size:8; signed:0;
225 field:gfp_t gfp_flags; offset:40; size:4; signed:0;
278 Dropped: 0
295 allowed for the table (normally 0, but if not a hint that you may
[all …]