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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-mc.yaml44 "^emc-timings-[0-9]+$":
53 "^timing-[0-9]+$":
114 reg = <0x70019000 0x1000>;
118 interrupts = <0 77 4>;
130 0x40040001 /* MC_EMEM_ARB_CFG */
131 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
132 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
133 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
134 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
135 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
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/kernel/linux/linux-5.10/tools/testing/selftests/kvm/include/x86_64/
Dsvm.h98 u64 avic_backing_page; /* Offset 0xe0 */
99 u8 reserved_6[8]; /* Offset 0xe8 */
100 u64 avic_logical_id; /* Offset 0xf0 */
101 u64 avic_physical_id; /* Offset 0xf8 */
106 #define TLB_CONTROL_DO_NOTHING 0
111 #define V_TPR_MASK 0x0f
120 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
134 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
150 #define SVM_VM_CR_VALID_MASK 0x001fULL
151 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
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/kernel/linux/linux-5.10/fs/cifs/
Dsmbfsctl.h44 #define FSCTL_DEVICE_DFS (0x0006 << 16)
45 #define FSCTL_DEVICE_FILE_SYSTEM (0x0009 << 16)
46 #define FSCTL_DEVICE_NAMED_PIPE (0x0011 << 16)
47 #define FSCTL_DEVICE_NETWORK_FILE_SYSTEM (0x0014 << 16)
48 #define FSCTL_DEVICE_MASK 0xffff0000
50 #define FSCTL_DEVICE_ACCESS_FILE_ANY_ACCESS (0x00 << 14)
51 #define FSCTL_DEVICE_ACCESS_FILE_READ_ACCESS (0x01 << 14)
52 #define FSCTL_DEVICE_ACCESS_FILE_WRITE_ACCESS (0x02 << 14)
53 #define FSCTL_DEVICE_ACCESS_FILE_READ_WRITE_ACCESS (0x03 << 14)
54 #define FSCTL_DEVICE_ACCESS_MASK 0x0000c000
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Dsmb2status.h26 * 0 1 2 3 4 5 6 7 8 9 0 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
32 #define STATUS_SEVERITY_SUCCESS __constant_cpu_to_le32(0x0000)
33 #define STATUS_SEVERITY_INFORMATIONAL cpu_to_le32(0x0001)
34 #define STATUS_SEVERITY_WARNING cpu_to_le32(0x0002)
35 #define STATUS_SEVERITY_ERROR cpu_to_le32(0x0003)
43 #define STATUS_SUCCESS cpu_to_le32(0x00000000)
44 #define STATUS_WAIT_0 cpu_to_le32(0x00000000)
45 #define STATUS_WAIT_1 cpu_to_le32(0x00000001)
46 #define STATUS_WAIT_2 cpu_to_le32(0x00000002)
47 #define STATUS_WAIT_3 cpu_to_le32(0x00000003)
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvif/
Dclass.h6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
10 #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
11 #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
13 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
14 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
15 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
16 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
18 #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
19 #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
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/kernel/linux/linux-5.10/arch/x86/include/asm/
Dsvm.h14 INTERCEPT_CR = 0,
24 /* Byte offset 000h (word 0) */
25 INTERCEPT_CR0_READ = 0,
143 u64 avic_backing_page; /* Offset 0xe0 */
144 u8 reserved_6[8]; /* Offset 0xe8 */
145 u64 avic_logical_id; /* Offset 0xf0 */
146 u64 avic_physical_id; /* Offset 0xf8 */
150 #define TLB_CONTROL_DO_NOTHING 0
155 #define V_TPR_MASK 0x0f
164 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
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Dcpufeatures.h28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
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/kernel/linux/linux-5.10/arch/x86/kvm/
Dcpuid.h51 [CPUID_1_EDX] = { 1, 0, CPUID_EDX},
52 [CPUID_8000_0001_EDX] = {0x80000001, 0, CPUID_EDX},
53 [CPUID_8086_0001_EDX] = {0x80860001, 0, CPUID_EDX},
54 [CPUID_1_ECX] = { 1, 0, CPUID_ECX},
55 [CPUID_C000_0001_EDX] = {0xc0000001, 0, CPUID_EDX},
56 [CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX},
57 [CPUID_7_0_EBX] = { 7, 0, CPUID_EBX},
58 [CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX},
59 [CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX},
60 [CPUID_6_EAX] = { 6, 0, CPUID_EAX},
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Dcpuid.c36 int feature_bit = 0; in xstate_required_size()
41 if (xstate_bv & 0x1) { in xstate_required_size()
43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); in xstate_required_size()
63 for (i = 0; i < nent; i++) { in cpuid_entry2_find()
82 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); in kvm_check_cpuid()
84 int vaddr_bits = (best->eax & 0xff00) >> 8; in kvm_check_cpuid()
86 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) in kvm_check_cpuid()
90 return 0; in kvm_check_cpuid()
97 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); in kvm_update_pv_runtime()
111 best = kvm_find_cpuid_entry(vcpu, 1, 0); in kvm_update_cpuid_runtime()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
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Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
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Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
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Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dcommon.c125 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
127 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
130 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
133 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
135 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
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/kernel/linux/linux-5.10/tools/arch/x86/include/asm/
Dcpufeatures.h28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
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/kernel/linux/linux-5.10/arch/x86/kvm/svm/
Dsvm.c72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
193 static bool __read_mostly dump_invalid_vmcb = 0;
213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
224 for (i = 0; i < NUM_MSR_MAPS; i++) { in svm_msrpm_offset()
254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr)); in invlpga()
305 return 0; in svm_set_efer()
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8822c_table.c16 0x80000015, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
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