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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
Dat91-natte.dtsi13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
60 #size-cells = <0>;
62 i2c@0 {
63 reg = <0>;
65 #size-cells = <0>;
69 reg = <0x9>;
81 #size-cells = <0>;
85 reg = <0x9>;
97 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dpoly1305-core.S_shipped29 mov x9,#0xfffffffc0fffffff
30 movk x9,#0x0fff,lsl#48
35 and x7,x7,x9 // &=0ffffffc0fffffff
36 and x9,x9,#-4
37 and x8,x8,x9 // &=0ffffffc0ffffffc
96 cmp x17,#0 // is_base2_26?
97 add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2)
116 mul x10,x5,x9 // h1*5*r1
117 umulh x11,x5,x9
130 mul x10,x6,x9 // h2*5*r1
[all …]
Dpoly1305-armv8.pl34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
78 mov $s1,#0xfffffffc0fffffff
79 movk $s1,#0x0fff,lsl#48
84 and $r0,$r0,$s1 // &=0ffffffc0fffffff
86 and $r1,$r1,$s1 // &=0ffffffc0ffffffc
145 cmp x17,#0 // is_base2_26?
233 cmp $r0,#0 // is_base2_26?
262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
[all …]
Dsha512-core.S_shipped74 add x29,sp,#0
97 rev x3,x3 // 0
175 eor x9,x21,x21,ror#23
181 eor x16,x16,x9,ror#18 // Sigma1(e)
182 ror x9,x25,#28
189 eor x17,x9,x17,ror#34 // Sigma0(a)
220 ldp x9,x10,[x1],#2*8
243 rev x9,x9 // 6
251 add x21,x21,x9 // h+=X[i]
394 str x7,[sp,#0]
[all …]
Daes-modes.S255 add x9, x8, #32
257 sub x9, x9, x4
259 ld1 {v4.16b}, [x9]
284 add x9, x8, #32
286 sub x9, x9, x4
288 ld1 {v4.16b}, [x9]
313 .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
314 .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
315 .byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
316 .byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf
[all …]
/kernel/linux/linux-5.10/arch/arm64/mm/
Dproc.S34 #define TCR_KASLR_FLAGS 0
45 #define TCR_KASAN_FLAGS 0
77 mrs x9, mdscr_el1
89 stp x8, x9, [x0, #48]
110 ldp x9, x10, [x0, #48]
130 msr vbar_el1, x9
209 tbz \type, #0, skip_\()\type // Skip invalid and
237 end_pudp .req x9
448 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
472 tcr_clear_errata_bits x10, x9, x5
[all …]
/kernel/linux/linux-5.10/arch/arm/crypto/
Dchacha-scalar-core.S14 * (x8, x9) to the stack and swap them out with (x10, x11). This adds one
24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such
38 X9_X11 .req r9 // shared by x9 and x11
49 and \t1, \in, #0xff00
50 and \t2, \in, #0xff0000
123 // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13)
126 // save (x8, x9); restore (x10, x11)
127 __strd X8_X10, X9_X11, sp, 0
141 // save (x10, x11); restore (x8, x9)
143 __ldrd X8_X10, X9_X11, sp, 0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]
Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_sh_mask.h7 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
8 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
9 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
10 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
11 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
12 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
13 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
14 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
16 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
17 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_0_sh_mask.h27 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
28 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
30 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
31 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
33 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0
34 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
36 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
37 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
39 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
40 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
[all …]
Dsdma0_4_1_sh_mask.h27 …UCODE_ADDR__VALUE__SHIFT 0x0
28 …DR__VALUE_MASK 0x00001FFFL
30 …UCODE_DATA__VALUE__SHIFT 0x0
31 …TA__VALUE_MASK 0xFFFFFFFFL
33 …VM_CNTL__CMD__SHIFT 0x0
34 …_CMD_MASK 0x0000000FL
36 …VM_CTX_LO__ADDR__SHIFT 0x2
37 …O__ADDR_MASK 0xFFFFFFFCL
39 …VM_CTX_HI__ADDR__SHIFT 0x0
40 …I__ADDR_MASK 0xFFFFFFFFL
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h28 ENDIAN_NONE = 0x0,
29 ENDIAN_8IN16 = 0x1,
30 ENDIAN_8IN32 = 0x2,
31 ENDIAN_8IN64 = 0x3,
34 ARRAY_LINEAR_GENERAL = 0x0,
35 ARRAY_LINEAR_ALIGNED = 0x1,
36 ARRAY_1D_TILED_THIN1 = 0x2,
37 ARRAY_1D_TILED_THICK = 0x3,
38 ARRAY_2D_TILED_THIN1 = 0x4,
39 ARRAY_PRT_TILED_THIN1 = 0x5,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h28 UVDFC_FENCE = 0x0,
29 UVDFC_TRAP = 0x1,
30 UVDFC_DECODED_ADDR = 0x2,
31 UVDFC_MBLOCK_ADDR = 0x3,
32 UVDFC_ITBUF_ADDR = 0x4,
33 UVDFC_DISPLAY_ADDR = 0x5,
34 UVDFC_EOD = 0x6,
35 UVDFC_DISPLAY_PITCH = 0x7,
36 UVDFC_DISPLAY_TILING = 0x8,
37 UVDFC_BITSTREAM_ADDR = 0x9,
[all …]
Duvd_5_0_enum.h28 UVDFC_FENCE = 0x0,
29 UVDFC_TRAP = 0x1,
30 UVDFC_DECODED_ADDR = 0x2,
31 UVDFC_MBLOCK_ADDR = 0x3,
32 UVDFC_ITBUF_ADDR = 0x4,
33 UVDFC_DISPLAY_ADDR = 0x5,
34 UVDFC_EOD = 0x6,
35 UVDFC_DISPLAY_PITCH = 0x7,
36 UVDFC_DISPLAY_TILING = 0x8,
37 UVDFC_BITSTREAM_ADDR = 0x9,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h27 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
28 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL
30 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
31 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
33 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0
34 #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
36 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
37 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
39 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
40 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_2_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x2c
34 #define RCU_SAM_RTL_BYTES 0x2c
35 #define RCU_SMU_BYTES 0x14
36 #define RCU_SMU_RTL_BYTES 0x14
[all …]
Dsmu_7_1_1_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x80
30 #define RCU_CCF_BITS0 0x1000
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x0
34 #define RCU_SAM_RTL_BYTES 0x0
35 #define RCU_SMU_BYTES 0x0
36 #define RCU_SMU_RTL_BYTES 0x0
[all …]
Dsmu_7_1_0_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x28
30 #define RCU_CCF_BITS0 0x500
31 #define RCU_CCF_DWORDS1 0x7f
32 #define RCU_CCF_BITS1 0x1000
33 #define RCU_SAM_BYTES 0x40
34 #define RCU_SAM_RTL_BYTES 0x40
35 #define KEYS_CHAIN_ADR 0x0
36 #define SAMU_KEY_SADR 0xa0
[all …]

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