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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_RF.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
24 pDM_Odm->CutVersion << 24 | in CheckPositive()
25 pDM_Odm->SupportPlatform << 16 | in CheckPositive()
26 pDM_Odm->PackageType << 12 | in CheckPositive()
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-pip-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
[all …]
Dcvmx-led-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
88 uint64_t reserved_1_63:63;
92 uint64_t reserved_1_63:63;
101 uint64_t reserved_1_63:63;
105 uint64_t reserved_1_63:63;
114 uint64_t reserved_1_63:63;
118 uint64_t reserved_1_63:63;
179 uint64_t reserved_32_63:32;
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dtable.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
2899 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
2900 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
2902 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
2903 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
2905 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
2906 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
2908 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
2909 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-event_source-devices-hv_gpci3 Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
4 Description: Read-only. Attribute group to describe the magic bits
6 (See ABI/testing/sysfs-bus-event_source-devices-format).
12 counter_info_version = "config:16-23"
13 length = "config:24-31"
14 partition_id = "config:32-63"
15 request = "config:0-31"
16 sibling_part_id = "config:32-63"
17 hw_chip_id = "config:32-63"
18 offset = "config:32-63"
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/kernel/linux/linux-5.10/drivers/net/ethernet/ibm/ehea/
Dehea_phyp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 while (((1U << ld) - 1) < queue_entries) in get_order_of_qentries()
25 return ld - 1; in get_order_of_qentries()
144 #define H_ALL_RES_QP_RES_TYP EHEA_BMASK_IBM(56, 63)
148 #define H_ALL_RES_QP_PD EHEA_BMASK_IBM(32, 63)
160 #define H_ALL_RES_QP_MAX_R3SGE EHEA_BMASK_IBM(61, 63)
165 #define H_ALL_RES_QP_PORT_NUM EHEA_BMASK_IBM(48, 63)
176 #define H_ALL_RES_QP_ACT_R2WQE EHEA_BMASK_IBM(32, 47)
177 #define H_ALL_RES_QP_ACT_R3WQE EHEA_BMASK_IBM(48, 63)
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Dehea_qmr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Jan-Bernd Themann <themann@de.ibm.com>
32 #define EHEA_HUGEPAGE_PFN_MASK ((EHEA_HUGEPAGE_SIZE - 1) >> PAGE_SHIFT)
40 * WQE - Work Queue Entry
41 * SWQE - Send Work Queue Entry
42 * RWQE - Receive Work Queue Entry
43 * CQE - Completion Queue Entry
44 * EQE - Event Queue Entry
45 * MR - Memory Region
56 #define EHEA_WR_ID_REFILL EHEA_BMASK_IBM(48, 63)
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/kernel/linux/linux-5.10/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
44 perspective, bit 63 always means bit offset 7 of byte 7, albeit only
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/kernel/linux/linux-5.10/drivers/net/ethernet/sfc/falcon/
Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * ef4_dword_t) to be little-endian.
34 #define EF4_DWORD_0_WIDTH 32
35 #define EF4_DWORD_1_LBN 32
36 #define EF4_DWORD_1_WIDTH 32
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dpsp_gfx_if.h46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
110 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
113 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
136 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
170 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
179 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
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/kernel/linux/linux-5.10/drivers/net/ethernet/sfc/
Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * efx_dword_t) to be little-endian.
34 #define EFX_DWORD_0_WIDTH 32
35 #define EFX_DWORD_1_LBN 32
36 #define EFX_DWORD_1_WIDTH 32
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Def10_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2012-2017 Solarflare Communications Inc.
13 * E<type>_<min-rev><max-rev>_
18 * -------------------------------------------------------------
23 * <min-rev> is the first revision to which the definition applies:
28 * then <max-rev> is the last revision to which the definition applies;
42 #define ERF_DZ_HW_REV_ID_WIDTH 32
49 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
54 #define ERF_DZ_ISR_REG_WIDTH 32
59 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
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/kernel/linux/linux-5.10/include/crypto/
Dgf128mul.h1 /* gf128mul.h - GF(2^128) multiplication functions
16 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
59 * http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf
61 * The elements of GF(2^128) := GF(2)[X]/(X^128-X^7-X^2-X^1-1) can
73 * in every byte in little-endian order and the bytes themselves also in
74 * little endian order. I will call this lle (little-little-endian).
81 * bytes also. This is bbe (big-big-endian). Now the buffer above
86 * Both of the above formats are easy to implement on big-endian
94 * The common machine word-size is smaller than 128 bits, so to make
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
5619 { 0, 0, 0, 0, 2, 32, },
5621 { 0, 0, 0, 0, 3, 32, },
5623 { 0, 0, 0, 0, 4, 32, },
5625 { 0, 0, 0, 0, 5, 32, },
5627 { 0, 0, 0, 0, 6, 32, },
5629 { 0, 0, 0, 0, 7, 32, },
5631 { 0, 0, 0, 0, 8, 32, },
5633 { 0, 0, 0, 0, 9, 32, },
[all …]
/kernel/linux/linux-5.10/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
34 * Many hardware clock counters are only 32 bits wide and therefore have
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
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/kernel/linux/linux-5.10/arch/s390/include/asm/
Dnmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MCIC_SUBCLASS_MASK (1ULL<<63 | 1ULL<<62 | 1ULL<<61 | \
23 #define MCCK_CODE_SYSTEM_DAMAGE BIT(63)
24 #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5)
25 #define MCCK_CODE_CP BIT(63 - 9)
26 #define MCCK_CODE_CPU_TIMER_VALID BIT(63 - 46)
27 #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20)
28 #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23)
29 #define MCCK_CODE_CR_VALID BIT(63 - 29)
30 #define MCCK_CODE_GS_VALID BIT(63 - 36)
[all …]
Dctl_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define CR0_CLOCK_COMPARATOR_SIGN BIT(63 - 10)
14 #define CR0_LOW_ADDRESS_PROTECTION BIT(63 - 35)
15 #define CR0_EMERGENCY_SIGNAL_SUBMASK BIT(63 - 49)
16 #define CR0_EXTERNAL_CALL_SUBMASK BIT(63 - 50)
17 #define CR0_CLOCK_COMPARATOR_SUBMASK BIT(63 - 52)
18 #define CR0_CPU_TIMER_SUBMASK BIT(63 - 53)
19 #define CR0_SERVICE_SIGNAL_SUBMASK BIT(63 - 54)
20 #define CR0_UNUSED_56 BIT(63 - 56)
21 #define CR0_INTERRUPT_KEY_SUBMASK BIT(63 - 57)
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/
Dmsc01_ic.h20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
40 #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41 #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42 #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43 #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
131 * Soc-it interrupts are configurable.
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
88 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
169 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
170 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
173 #define Q_ENT(q, p) ((q)->base + \
174 Q_IDX(&((q)->llq), p) * \
175 (q)->ent_dwords)
185 #define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1)
214 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
244 #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
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/kernel/linux/linux-5.10/drivers/staging/media/ipu3/
Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
10 /* Scale factor 32 / (32 + 0) = 1 */
22 /* Scale factor 32 / (32 + 1) = 0.969697 */
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/rkvdec/
Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
83 #define SCALING_LIST_ADDRESS PS_FIELD(184, 32)
86 #define DPB_OFFS(i, j) (288 + ((j) * 32 * 7) + ((i) * 7))
136 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
137 CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
140 CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
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/kernel/linux/linux-5.10/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
[all …]
/kernel/linux/linux-5.10/drivers/crypto/cavium/cpt/
Dcpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
42 * Address must be 16-byte aligned.
43 * Bits <63:49> are ignored by hardware; software should use a
44 * sign-extended bit <48> for forward compatibility.
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
52 * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
56 * work-queue entry that CPT submits work to SSO after all context,
59 * Bits <63:49> are ignored by hardware; software should
[all …]
/kernel/linux/linux-5.10/arch/powerpc/perf/
Dhv-gpci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #define pr_fmt(fmt) "hv-gpci: " fmt
18 #include "hv-gpci.h"
19 #include "hv-common.h"
23 * perf stat -e 'hv_gpci/counter_info_version=3,offset=0,length=8,
34 * used depends on the event. See REQUEST_IDX_KIND in hv-gpci-requests.h
36 EVENT_DEFINE_RANGE_FORMAT(starting_index, config, 32, 63);
37 EVENT_DEFINE_RANGE_FORMAT_LITE(phys_processor_idx, config, 32, 63);
38 EVENT_DEFINE_RANGE_FORMAT_LITE(sibling_part_id, config, 32, 63);
39 EVENT_DEFINE_RANGE_FORMAT_LITE(hw_chip_id, config, 32, 63);
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt7622.txt4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]

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