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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/
Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_dsp.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
41 * \brief Functions that generate RISC-V DSP SIMD instructions.
44 …* The following functions generate specified RISC-V SIMD instructions that cannot be directly acce…
47 * - r.H == rH1: r[31:16], r.L == r.H0: r[15:0]
48 * - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0]
49 * - r.B[x]: r[(x*8+7):(x*8+0)]
50 * - r.H[x]: r[(x*16+7):(x*16+0)]
51 * - r.W[x]: r[(x*32+31):(x*32+0)]
52 …* - r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains thi…
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/kernel/linux/linux-5.10/include/linux/
Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * @dividend: unsigned 64bit dividend
17 * @divisor: unsigned 32bit divisor
18 * @remainder: pointer to unsigned 32bit remainder
22 * This is commonly provided by 32bit archs to provide an optimized 64bit
32 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
33 * @dividend: signed 64bit dividend
34 * @divisor: signed 32bit divisor
35 * @remainder: pointer to signed 32bit remainder
[all …]
Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
[all …]
/kernel/linux/linux-5.10/arch/s390/include/asm/
Delf.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Derived from "include/asm-i386/elf.h"
13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-u300.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2009 ST-Ericsson AB
35 /* Reset OS Timer 32bit (-/W) */
38 /* Enable OS Timer 32bit (-/W) */
41 /* Disable OS Timer 32bit (-/W) */
44 /* OS Timer Mode Register 32bit (-/W) */
48 /* OS Timer Status Register 32bit (R/-) */
59 /* OS Timer Current Count Register 32bit (R/-) */
61 /* OS Timer Terminal Count Register 32bit (R/W) */
63 /* OS Timer Interrupt Enable Register 32bit (-/W) */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
[all …]
/kernel/linux/linux-5.10/lib/
Diomap_copy.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
15 * Copy data from kernel space to MMIO space, in units of 32 bits at a
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
[all …]
/kernel/liteos_a/arch/arm/gic/
Dgic_v3.c2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
45 return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) | /* 3: Serial number, 32: Register bit offset */ in MpidrToAffinity()
46 (MPIDR_AFF_LEVEL(mpidr, 2) << 16) | /* 2: Serial number, 16: Register bit offset */ in MpidrToAffinity()
47 (MPIDR_AFF_LEVEL(mpidr, 1) << 8) | /* 1: Serial number, 8: Register bit offset */ in MpidrToAffinity()
86 cpu--; in GicTargetList()
109 … val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) | /* 3: Serial number, 48: Register bit offset */ in GicSgi()
110 … (MPIDR_AFF_LEVEL(cluster, 2) << 32) | /* 2: Serial number, 32: Register bit offset */ in GicSgi()
111 … (MPIDR_AFF_LEVEL(cluster, 1) << 16) | /* 1: Serial number, 16: Register bit offset */ in GicSgi()
112 (irq << 24) | tList); /* 24: Register bit offset */ in GicSgi()
[all …]
/kernel/linux/linux-5.10/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
7 config 64BIT
10 config 32BIT config
33 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
39 select GENERIC_ATOMIC64 if !64BIT
52 select GENERIC_TIME_VSYSCALL if MMU && 64BIT
57 select HAVE_ARCH_KASAN if MMU && 64BIT
70 select HAVE_GENERIC_VDSO if MMU && 64BIT
93 default 18 if 64BIT
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/ipu3/
Dipu3-abi.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include "include/intel-ipu3.h"
15 #define IMGU_DVS_BLOCK_H 32
31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32
32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32
46 #define IMGU_PM_CTRL_START BIT(0)
47 #define IMGU_PM_CTRL_CFG_DONE BIT(1)
48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2)
49 #define IMGU_PM_CTRL_NACK_ALL BIT(3)
50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4)
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dswab.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
71 __u32 h = val >> 32; in __fswab64()
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
140 #else /* __BITS_PER_LONG == 32 */ in __swab()
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/
Dhighuid.rst2 Notes on the change from 16-bit UIDs to 32-bit UIDs
8 - kernel code MUST take into account __kernel_uid_t and __kernel_uid32_t
12 - kernel code should use uid_t and gid_t in kernel-private structures and
15 What's left to be done for 32-bit UIDs on all Linux architectures:
17 - Disk quotas have an interesting limitation that is not related to the
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
25 - Decide whether or not to keep backwards compatibility with the system
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
[all …]
/kernel/linux/linux-5.10/fs/ext4/
Dinode-test.c1 // SPDX-License-Identifier: GPL-2.0
28 #define LOWER_MSB_1 (-(UPPER_MSB_0) - 1L) /* avoid overflow */
33 #define UPPER_MSB_1 (-1L)
38 #define MAX_NANOSECONDS ((1L << 30) - 1)
43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits"
45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits"
47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits"
49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits"
51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on"
53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on"
[all …]
/kernel/linux/linux-5.10/arch/s390/kernel/
Dmodule.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <asm/nospec-branch.h>
54 mod->state == MODULE_STATE_LIVE) in module_arch_freeing_init()
57 vfree(mod->arch.syminfo); in module_arch_freeing_init()
58 mod->arch.syminfo = NULL; in module_arch_freeing_init()
65 info = me->arch.syminfo + ELF_R_SYM (rela->r_info); in check_rela()
66 switch (ELF_R_TYPE (rela->r_info)) { in check_rela()
67 case R_390_GOT12: /* 12 bit GOT offset. */ in check_rela()
68 case R_390_GOT16: /* 16 bit GOT offset. */ in check_rela()
69 case R_390_GOT20: /* 20 bit GOT offset. */ in check_rela()
[all …]
/kernel/linux/linux-5.10/Documentation/staging/
Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
28 the best error-detecting properties, this should correspond to the
[all …]
/kernel/linux/linux-5.10/arch/ia64/lib/
Dchecksum.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1999, 2003 Hewlett-Packard Co
11 * in an architecture-specific manner due to speed..
22 /* add up 32-bit words for 33 bits */ in from64to16()
23 x = (x & 0xffffffff) + (x >> 32); in from64to16()
24 /* add up 16-bit and 17-bit words for 17+c bits */ in from64to16()
26 /* add up 16-bit and 2-bit for 16+c bit */ in from64to16()
34 * computes the checksum of the TCP/UDP pseudo-header
35 * returns a 16-bit checksum, already complemented.
57 /* Fold down to 32-bits so we don't lose in the typedef-less network stack. */ in csum_tcpudp_nofold()
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/powerpc/vphn/
Dtest-vphn.c1 // SPDX-License-Identifier: GPL-2.0
41 "vphn: 1 x 16-bit value",
56 "vphn: 2 x 16-bit values",
72 "vphn: 3 x 16-bit values",
89 "vphn: 4 x 16-bit values",
107 /* Parsing the next 16-bit value out of the next 64-bit input
110 "vphn: 5 x 16-bit values",
129 /* Parse at most 6 x 64-bit input values */
130 "vphn: 24 x 16-bit values",
168 "vphn: 1 x 32-bit value",
[all …]
/kernel/linux/linux-5.10/lib/math/
Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
13 * The fast case for (n>>32 == 0) is handled inline by do_div().
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
25 /* Not needed on 64bit architectures */
26 #if BITS_PER_LONG == 32
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
[all …]
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
34 * r0-r30: 64 bit
35 * sp,pc : 64 bit
36 * pstate : 32 bit
39 * f0-f31: 128 bit
40 * fpsr & fpcr: 32 bit
41 * Total: 32 + 2
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
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