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/kernel/linux/linux-5.10/tools/power/x86/intel-speed-select/
Disst-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
9 int isst_write_pm_config(int cpu, int cp_state) in isst_write_pm_config() argument
19 ret = isst_send_mbox_command(cpu, WRITE_PM_CONFIG, PM_FEATURE, 0, req, in isst_write_pm_config()
24 debug_printf("cpu:%d WRITE_PM_CONFIG resp:%x\n", cpu, resp); in isst_write_pm_config()
29 int isst_read_pm_config(int cpu, int *cp_state, int *cp_cap) in isst_read_pm_config() argument
34 ret = isst_send_mbox_command(cpu, READ_PM_CONFIG, PM_FEATURE, 0, 0, in isst_read_pm_config()
39 debug_printf("cpu:%d READ_PM_CONFIG resp:%x\n", cpu, resp); in isst_read_pm_config()
47 int isst_get_ctdp_levels(int cpu, struct isst_pkg_ctdp *pkg_dev) in isst_get_ctdp_levels() argument
52 ret = isst_send_mbox_command(cpu, CONFIG_TDP, in isst_get_ctdp_levels()
[all …]
/kernel/linux/linux-5.10/arch/mips/netlogic/xlr/
Dfmn-config.c2 * Copyright (c) 2003-2012 Broadcom Corporation
35 #include <asm/cpu-info.h>
39 #include <asm/cpu.h>
56 xlr_board_fmn_config.bucket_size[(bkt * 8) + 0], in print_credit_config()
57 xlr_board_fmn_config.bucket_size[(bkt * 8) + 1], in print_credit_config()
58 xlr_board_fmn_config.bucket_size[(bkt * 8) + 2], in print_credit_config()
59 xlr_board_fmn_config.bucket_size[(bkt * 8) + 3], in print_credit_config()
60 xlr_board_fmn_config.bucket_size[(bkt * 8) + 4], in print_credit_config()
61 xlr_board_fmn_config.bucket_size[(bkt * 8) + 5], in print_credit_config()
62 xlr_board_fmn_config.bucket_size[(bkt * 8) + 6], in print_credit_config()
[all …]
/kernel/linux/linux-5.10/arch/mips/kernel/
Dsmp-bmips.c20 #include <linux/cpu.h>
39 #include <asm/cpu-features.h>
52 static void bmips_set_reset_vec(int cpu, u32 val);
56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
69 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
70 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
71 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
72 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include "exynos5422-odroid-core.dtsi"
15 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 compatible = "pwm-leds";
24 pwm-names = "pwm2";
25 max-brightness = <255>;
26 linux,default-trigger = "heartbeat";
30 thermal-zones {
31 cpu0_thermal: cpu0-thermal {
[all …]
Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&power_key>;
32 debounce-interval = <0>;
33 wakeup-source;
38 pinctrl-0 = <&emmc_nrst_pin>;
[all …]
/kernel/linux/linux-5.10/arch/x86/kernel/
Dmsr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ----------------------------------------------------------------------- *
4 * Copyright 2000-2008 H. Peter Anvin - All Rights Reserved
7 * ----------------------------------------------------------------------- */
13 * and then read/write in chunks of 8 bytes. A larger size means multiple
16 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
17 * an SMP box will direct the access to CPU %d.
33 #include <linux/cpu.h>
59 int cpu = iminor(file_inode(file)); in msr_read() local
63 if (count % 8) in msr_read()
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/kernel/linux/linux-5.10/tools/perf/util/
Dcpumap.c1 // SPDX-License-Identifier: GPL-2.0
25 map = perf_cpu_map__empty_new(cpus->nr); in cpu_map__from_entries()
29 for (i = 0; i < cpus->nr; i++) { in cpu_map__from_entries()
31 * Special treatment for -1, which is not real cpu number, in cpu_map__from_entries()
32 * and we need to use (int) -1 to initialize map[i], in cpu_map__from_entries()
35 if (cpus->cpu[i] == (u16) -1) in cpu_map__from_entries()
36 map->map[i] = -1; in cpu_map__from_entries()
38 map->map[i] = (int) cpus->cpu[i]; in cpu_map__from_entries()
48 int nr, nbits = mask->nr * mask->long_size * BITS_PER_BYTE; in cpu_map__from_mask()
50 nr = bitmap_weight(mask->mask, nbits); in cpu_map__from_mask()
[all …]
Dsvghelper.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * svghelper.c - helper functions for outputting svg
43 static double cpu2slot(int cpu) in cpu2slot() argument
45 return 2 * cpu + 1; in cpu2slot()
50 static double cpu2y(int cpu) in cpu2y() argument
53 return cpu2slot(topology_map[cpu]) * SLOT_MULT; in cpu2y()
55 return cpu2slot(cpu) * SLOT_MULT; in cpu2y()
62 X = 1.0 * svg_page_width * (__time - first_time) / (last_time - first_time); in time2pixels()
77 while (loop--) { in round_text_size()
102 new_width = (last_time - first_time) / 5000000; in open_svg()
[all …]
Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
14 int sz = cpu__max_cpu() + 8 - 1; in get_cpu_set_size()
21 return sz / 8; in get_cpu_set_size()
28 a->orig_cpus = bitmap_alloc(cpu_set_size * 8); in affinity__setup()
29 if (!a->orig_cpus) in affinity__setup()
30 return -1; in affinity__setup()
31 sched_getaffinity(0, cpu_set_size, (cpu_set_t *)a->orig_cpus); in affinity__setup()
32 a->sched_cpus = bitmap_alloc(cpu_set_size * 8); in affinity__setup()
33 if (!a->sched_cpus) { in affinity__setup()
34 zfree(&a->orig_cpus); in affinity__setup()
[all …]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Routines to identify caches on Intel CPU.
7 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
13 #include <linux/cpu.h>
24 #include "cpu.h"
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
[all …]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
Ddove.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
18 #include "dove-divider.h"
23 * Dove PLL sample-at-reset configuration
25 * SAR0[8:5] : CPU frequency
29 * 8 = 800 MHz
39 * SAR0[11:9] : CPU to L2 Clock divider ratio
40 * 0 = (1/1) * CPU
41 * 2 = (1/2) * CPU
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
[all …]
/kernel/linux/linux-5.10/tools/power/x86/x86_energy_perf_policy/
Dx86_energy_perf_policy.81 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
3 .TH X86_ENERGY_PERF_POLICY 8
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
[all …]
/kernel/linux/linux-5.10/arch/alpha/kernel/
Dcore_mcpcia.c1 // SPDX-License-Identifier: GPL-2.0
7 * Code common to all MCbus-PCI Adaptor core logic chipsets
27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
33 * BIOS32-style PCI interface:
54 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
55 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
57 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * 10:8 Function number
66 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
Dcore_t2.c1 // SPDX-License-Identifier: GPL-2.0
37 * By default, we direct-map starting at 2GB, in order to allow the
38 * maximum size direct-map window (2GB) to match the maximum amount of
40 * floppy to DMA only via the scatter/gather window set up for 8MB
41 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
43 * For now, this seems a reasonable trade-off: even though most SABLEs
62 * NOTE: Herein lie back-to-back mb instructions. They are magic.
68 * BIOS32-style PCI interface:
108 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
/kernel/linux/linux-5.10/tools/power/cpupower/debug/i386/
Dcentrino-decode.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2003 - 2004 Dominik Brodowski <linux@dominikbrodowski.de>
6 * linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
9 * USAGE: simply run it to decode the current settings on CPU 0,
10 * or pass the CPU number as argument, or pass the MSR content
28 static int rdmsr(unsigned int cpu, unsigned int msr, in rdmsr() argument
34 int retval = -1; in rdmsr()
38 if (cpu > MCPU) in rdmsr()
41 sprintf(file, "/dev/cpu/%d/msr", cpu); in rdmsr()
47 if (lseek(fd, msr, SEEK_CUR) == -1) in rdmsr()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt6755.dtsi14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
33 device_type = "cpu";
[all …]
Dmt6795.dtsi14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
33 device_type = "cpu";
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dcputhreads.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * as the CPU numbers are still allocated, just not brought online).
35 /* cpu_thread_mask_to_cores - Return a cpumask of one per cores
40 * This function returns a cpumask which will have one online cpu's
49 int i, cpu; in cpu_thread_mask_to_cores() local
55 cpu = cpumask_next_and(-1, &tmp, cpu_online_mask); in cpu_thread_mask_to_cores()
56 if (cpu < nr_cpu_ids) in cpu_thread_mask_to_cores()
57 cpumask_set_cpu(cpu, &res); in cpu_thread_mask_to_cores()
74 int cpu_core_index_of_thread(int cpu);
77 static inline int cpu_core_index_of_thread(int cpu) { return cpu; } in cpu_core_index_of_thread() argument
[all …]
/kernel/linux/linux-5.10/arch/x86/include/asm/
Dsegment.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
15 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
24 #define __BOOT_CS (GDT_ENTRY_BOOT_CS*8)
25 #define __BOOT_DS (GDT_ENTRY_BOOT_DS*8)
26 #define __BOOT_TSS (GDT_ENTRY_BOOT_TSS*8)
60 * The layout of the per-CPU GDT under Linux:
62 * 0 - null <=== cacheline #1
63 * 1 - reserved
64 * 2 - reserved
[all …]
/kernel/linux/linux-5.10/tools/power/x86/intel_pstate_tracer/
Dintel_pstate_tracer.py2 # SPDX-License-Identifier: GPL-2.0-only
3 # -*- coding: utf-8 -*-
7 - If there is Linux trace file with pstate_sample events enabled, then
9 - If user has not specified a trace file as input via command line parameters,
16 gnuplot-py 1.8 or higher
18 gnuplot-py, phython-gnuplot or phython3-gnuplot, gnuplot-nox, ... )
20 HWP (Hardware P-States are disabled)
57 C_MPERF = 8
79 print(' ./intel_pstate_tracer.py [-c cpus] -t <trace_file> -n <test_name>')
81 … print(' ./intel_pstate_tracer.py [--cpu cpus] ---trace_file <trace_file> --name <test_name>')
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
D4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2002-2005 MontaVista Software Inc.
34 memsize -= 4096; in chip_11_errata()
126 #define DDR0_08 8
140 #define DDR_MAX_ROW_REG_SHIFT 8
146 #define DDR_CS_MAP_SHIFT 8
155 #define DDR_COL_SZ_SHIFT 8
162 * Some U-Boot versions set the number of chipselects to two
181 model[sizeof(model)-1] = 0; in ibm4xx_denali_get_cs()
228 dpath = 8; /* 64 bits */ in ibm4xx_denali_fixup_memsize()
[all …]
/kernel/linux/linux-5.10/drivers/leds/trigger/
Dledtrig-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ledtrig-cpu.c - LED trigger based on CPU activity
5 * This LED trigger will be registered for first 8 CPUs and named
6 * as cpu0..cpu7. There's additional trigger called cpu that
7 * is on when any CPU is active.
10 * with additional sysfs file selecting which CPU to watch.
15 * An API named ledtrig_cpu is exported for any user, who want to add CPU
19 * Copyright 2011 - 2012 Bryan Wu <bryan.wu@canonical.com>
28 #include <linux/cpu.h>
31 #define MAX_NAME_LEN 8
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/
Dmicrodev.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/include/asm-sh/microdev.h
7 * Definitions for the SuperH SH4-202 MicroDev board.
17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
20 * correctly route - unfortunately, they have the same name and
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 … MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on …
26 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
[all …]
/kernel/linux/linux-5.10/arch/mips/mm/
Dtlb-r3k.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <asm/cpu.h>
49 write_c0_index(entry << 8); in local_flush_tlb_from()
65 local_flush_tlb_from(r3k_have_wired_reg ? read_c0_wired() : 8); in local_flush_tlb_all()
73 struct mm_struct *mm = vma->vm_mm; in local_flush_tlb_range()
74 int cpu = smp_processor_id(); in local_flush_tlb_range() local
76 if (cpu_context(cpu, mm) != 0) { in local_flush_tlb_range()
81 cpu_context(cpu, mm) & asid_mask, start, end); in local_flush_tlb_range()
84 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; in local_flush_tlb_range()
87 int newpid = cpu_context(cpu, mm) & asid_mask; in local_flush_tlb_range()
[all …]

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