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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml18 Secondary GICs are cascaded into the upward interrupt controller and do not
105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
/kernel/linux/linux-5.10/include/linux/irqchip/
Darm-gic.h144 * chips and call this to register their GICs.
/kernel/linux/linux-5.10/drivers/perf/
Darm_pmu_acpi.c47 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
/kernel/linux/linux-5.10/Documentation/arm64/
Dacpi_object_usage.rst629 MADT for GICs are expected to be in synchronization. The _UID of the Device
698 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-gic.c504 * because any nested/secondary GICs do not directly interface in gic_cpu_init()
1218 * For primary GICs, skip over SGIs. in gic_init_bases()