| /kernel/linux/linux-5.10/Documentation/virt/kvm/devices/ |
| D | arm-vgic.rst | 17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
58 GICv2 specs. Getting or setting such a register has the same effect as
65 GICv2 is changed in a way directly observable by the guest or userspace.
92 defined in the GICv2 specs. Getting or setting such a register has the
96 fixed format for our implementation that fits with the model of a "GICv2
112 similar to GICv2's GICH_APR.
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| D | arm-vgic-v3.rst | 14 possible to create both a GICv3 and GICv2 on the same VM.
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| /kernel/linux/linux-5.10/include/kvm/ |
| D | arm_vgic.h | 37 VGIC_V2, /* Good ol' GICv2 */
65 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
120 u8 targets; /* GICv2 target VCPUs mask */
123 u8 source; /* GICv2 SGIs only */
124 u8 active_source; /* GICv2 SGIs only */
208 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
214 /* Userspace can write to GICv2 IGROUPR */
225 /* either a GICv2 CPU interface */
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-psci.dts | 4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)
8 #include "foundation-v8-gicv2.dtsi"
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| D | foundation-v8.dts | 5 * ARMv8 Foundation model DTS (GICv2 configuration)
9 #include "foundation-v8-gicv2.dtsi"
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| D | foundation-v8-gicv2.dtsi | 4 * ARMv8 Foundation model DTS (GICv2 configuration)
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| /kernel/liteos_a/arch/arm/gic/ |
| D | gic_v2.c | 165 * gicv2 valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM in HalIrqHandler()
188 case GICV2: in HalIrqVersion()
189 irqVerString = "GICv2"; in HalIrqVersion()
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| /kernel/linux/linux-5.10/arch/arm64/kvm/vgic/ |
| D | vgic-mmio-v2.c | 20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1
359 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr()
371 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()
385 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr()
397 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
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| D | vgic-init.c | 33 * structures. Can be executed lazily for GICv2.
81 * which had no chance yet to check the availability of the GICv2 in kvm_vgic_create()
147 * initialization when using a virtual GICv2. in kvm_vgic_dist_init()
390 * is a GICv2. A GICv3 must be explicitly initialized by the guest using the
401 * for the legacy case of a GICv2. Any other type must in vgic_lazy_init()
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| D | vgic-v3.c | 283 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable()
618 kvm_err("Cannot register GICv2 KVM device.\n"); in vgic_v3_probe()
631 kvm_info("disabling GICv2 emulation\n"); in vgic_v3_probe()
658 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in vgic_v3_load()
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| D | vgic-mmio.c | 342 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
434 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
461 * For GICv2 private interrupts we don't have to do anything because
563 * The GICv2 architecture indicates that the source CPUID for in vgic_mmio_change_active()
571 * for a GICv2 VM on some GIC implementations. Oh well. in vgic_mmio_change_active()
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| D | vgic-v2.c | 209 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_populate_lr()
406 kvm_err("Cannot register GICv2 KVM device\n"); in vgic_v2_probe()
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| D | vgic-debug.c | 149 seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); in print_dist_state()
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| D | vgic.h | 132 * state to userspace can generate either GICv2 or GICv3 CPU interface
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| D | vgic.c | 772 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
845 * GICv2 can always be accessed from the kernel because it is in can_access_vgic_from_kernel()
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-gic.c | 1285 name = kasprintf(GFP_KERNEL, "GICv2"); in __gic_init_bases()
1351 * first page of a GICv2. in gic_check_eoimode()
1357 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1366 * The first page was that of a GICv2, and in gic_check_eoimode()
1368 * to be a GICv2, and update the mapping. in gic_check_eoimode()
1370 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1378 * We detected *two* initial GICv2 pages in a in gic_check_eoimode()
1379 * row. Could be a GICv2 aliased over two 64kB in gic_check_eoimode()
1387 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1395 * Verify that we have the first 4kB of a GICv2 in gic_check_eoimode()
[all …]
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| /kernel/liteos_a/arch/arm/include/ |
| D | gic_common.h | 42 GICV2, enumerator
68 #define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4) /* GICv2 Interrupt Set-Acti…
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 93 For GICv2 with virtualization extensions, additional regions are
194 // GICv2
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm2711.dtsi | 13 interrupt-parent = <&gicv2>;
56 gicv2: interrupt-controller@40041000 { label
538 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
540 <0 0 0 2 &gicv2 GIC_SPI 144
542 <0 0 0 3 &gicv2 GIC_SPI 145
544 <0 0 0 4 &gicv2 GIC_SPI 146
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-xgene-sb.txt | 12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | brcm,stb-pcie.yaml | 132 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 205 - 设备树（DT）或 ACPI 表必须描述一个 GICv2 中断控制器。
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| /kernel/linux/linux-5.10/include/linux/irqchip/ |
| D | arm-gic-v3.h | 50 * Those registers are actually from GICv2, but the spec demands that they
594 /* These are for GICv2 emulation only */
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | memory.rst | 102 GICv2 gets mapped next to the HYP idmap page, as do vectors when
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| D | booting.rst | 241 - The DT or ACPI tables must describe a GICv2 interrupt controller.
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