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Searched full:harts (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/arch/riscv/kernel/
Dsbi.c97 * sbi_shutdown() - Remove all the harts from executing supervisor code.
363 * @hart_mask: A cpu mask containing all the target harts.
374 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
375 * @hart_mask: A cpu mask containing all the target harts.
388 * harts for the specified virtual address range.
389 * @hart_mask: A cpu mask containing all the target harts.
406 * remote harts for a virtual address range belonging to a specific ASID.
408 * @hart_mask: A cpu mask containing all the target harts.
427 * harts for the specified guest physical address range.
428 * @hart_mask: A cpu mask containing all the target harts.
[all …]
Dhead.S180 /* We lack SMP support or have too many harts, so park this hart */
/kernel/linux/linux-5.10/arch/riscv/mm/
Dcacheflush.c31 * informs the remote harts they need to flush their local instruction caches.
34 * IPIs for harts that are not currently executing a MM context and instead
54 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
Dcontext.c15 * shoot downs, so instead we send an IPI that informs the remote harts they
18 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
/kernel/linux/linux-5.10/arch/csky/abiv2/
Dcacheflush.c74 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt23 a PLIC interrupt property will typically list the HLICs for all present HARTs
Dsifive,plic-1.0.0.yaml17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/
Dcpus.yaml23 having four harts.
/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-riscv.c41 * It is guaranteed that all the timers across all the harts are synchronized