Searched full:mx1 (Results 1 – 25 of 30) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pllv1.c | 18 * PLL clock version 1, found on i.MX1/21/25/27/31/35
67 * frequency. PLLs with this register layout can be found on i.MX1, in clk_pllv1_recalc_rate()
85 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit in clk_pllv1_recalc_rate()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx1-clock.yaml | 7 title: Clock bindings for Freescale i.MX1 CPUs
15 for the full list of i.MX1 clock IDs.
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | Kconfig | 73 bool "i.MX1 support"
78 This enables support for Freescale i.MX1 processor
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| D | mach-imx1.c | 35 DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
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| D | hardware.h | 40 * mx1:
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| /kernel/linux/linux-5.10/include/soc/imx/ |
| D | timer.h | 10 GPT_TYPE_IMX1, /* i.MX1 */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | imx-pwm.yaml | 15 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx1-ads.dts | 10 model = "Freescale MX1 ADS";
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| D | imx1-pinfunc.h | 29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | imx2_wdt.c | 11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
13 * MX1: MX2+:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | imx-weim.txt | 57 For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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| /kernel/linux/linux-5.10/drivers/soc/imx/ |
| D | soc-imx.c | 57 soc_id = "i.MX1"; in imx_soc_device_init()
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-imx-gpt.c | 23 * - MX1/MXL
34 /* MX1, MX21, MX27 */
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | Kconfig | 207 tristate "i.MX1 PWM support"
210 Generic PWM framework driver for i.MX1 and i.MX21
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-mxc.c | 28 IMX1_GPIO, /* runs on i.mx1 */
277 /* MX1 and MX3 has one interrupt *per* gpio port */
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| /kernel/linux/linux-5.10/drivers/bus/ |
| D | imx-weim.c | 66 /* i.MX1/21 */
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| /kernel/linux/linux-5.10/drivers/pinctrl/freescale/ |
| D | pinctrl-imx1.c | 3 // i.MX1 pinctrl driver based on imx pinmux core
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| D | pinctrl-imx1-core.c | 36 * MX1 register offsets
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | mxcmmc.c | 6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | Kconfig | 267 Freescale i.MX1/21/27 chips.
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | imx.c | 54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
2426 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later in imx_uart_probe()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | fsl.yaml | 18 - description: i.MX1 based Boards
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| /kernel/linux/linux-5.10/arch/arm/ |
| D | Kconfig.debug | 382 bool "i.MX1 Debug UART"
386 on i.MX1.
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | sm501.c | 173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0019_linux_drivers_gpio.patch | 172 IMX1_GPIO, /* runs on i.mx1 */
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