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15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …35 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…60 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…75 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on t…80 …The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the …95 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…135 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or…150 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…[all …]
30 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…80 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the …90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…95 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the …100 …eing held at dispatch because it lost arbitration onto the issue pipe to another instruction (from…145 … from beyond the local L3. The source could be local/remote/distant memory or another core's cache"160 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…190 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…235 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…[all …]
10 … the core's L3 data cache. The source could be local/remote/distant memory or another core's cache"20 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the …25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…70 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …95 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on …100 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …180 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…185 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the …190 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…[all …]
25 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group…40 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on t…50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …55 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …100 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…
5 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the …50 …n": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on …115 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the …155 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L…170 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…195 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …280 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…315 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …330 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…335 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…[all …]
50 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on …205 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L…225 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…320 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…385 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…510 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the …565 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…735 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …840 …n": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on …910 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on t…[all …]
35 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…41 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or…47 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…53 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L…59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…77 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…251 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…257 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…[all …]
89 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…90 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…95 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…96 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…203 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a…204 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a…[all …]
371 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…372 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…377 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…378 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…401 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …402 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …[all …]
5 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…6 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…107 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…108 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…113 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…114 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…[all …]
29 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…35 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…107 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…113 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on t…119 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…125 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…131 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…35 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…36 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…41 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…42 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…95 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…101 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …107 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
21 …nd are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"28 …ued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"49 …PU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"56 … issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"77 …nd are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"84 …ued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"105 …nd are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"112 …ued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
12 "BriefDescription": "The number of all operations received by the HHA from another socket",13 "PublicDescription": "The number of all operations received by the HHA from another socket",19 …"BriefDescription": "The number of all operations received by the HHA from another SCCL in this so…20 …"PublicDescription": "The number of all operations received by the HHA from another SCCL in this s…
188 /* Restart another partition */196 /* Boot another partition */200 /* Stop this or another partition */204 /* Copy data from one partition to another */212 /* Get a property from another guest's device tree */216 /* Set a property in another guest's device tree */
49 check_err $? "Failed to create another clsact with ingress shared block"54 check_fail $? "Incorrect success to create another clsact with egress shared block"59 …check_err $? "Failed to create another clsact with egress shared block after blocker drop rule rem…68 check_err $? "Failed to create another clsact with egress shared block"98 check_err $? "Failed to create another clsact with ingress shared block"103 check_fail $? "Incorrect success to create another clsact with egress shared block"108 …check_err $? "Failed to create another clsact with egress shared block after blocker redirect rule…118 check_err $? "Failed to create another clsact with egress shared block"
60 PF device is being recovered in another guest.66 another message is sent to the guests to re-enable the VFs.79 PF device is being recovered in another guest.85 another message is sent to the guests to re-enable the VFs.
10 otherwise convert video data from one format into another format, in memory.27 the hardware and reprogram it whenever another file handler gets access.30 file handle is visible through another file handle).
20 * Context switch from one thread to another. If the two threads have49 * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can51 * the latest fph state from another CPU. In other words: eager save, lazy restore.
3 Do not affect user-assigned choice value by another choice.6 the defconfig result of a choice could be affected by another choice