| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 "Unit": "CPU-M-CF",
28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
31 "Unit": "CPU-M-CF",
35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
10 "Unit": "CPU-M-CF",
14 …on": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …: "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced fr…
10 "Unit": "CPU-M-CF",
14 … "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced fr…
17 "Unit": "CPU-M-CF",
21 …Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that i…
24 "Unit": "CPU-M-CF",
28 … Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that…
31 "Unit": "CPU-M-CF",
35 …Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
27 /* per-cpu object for tracking:
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
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|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | cache.json | 42 "PublicDescription": "Level 1 instruction cache refill",
45 "BriefDescription": "L1I cache refill"
48 "PublicDescription": "Level 1 instruction TLB refill",
54 "PublicDescription": "Level 1 data cache refill",
57 "BriefDescription": "L1D cache refill"
60 "PublicDescription": "Level 1 data cache access",
63 "BriefDescription": "L1D cache access"
66 "PublicDescription": "Level 1 data TLB refill",
72 "PublicDescription": "Level 1 instruction cache access",
75 "BriefDescription": "L1I cache access"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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|
| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group()
23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group()
27 static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) in get_cacheinfo() argument
32 * that cores have a homonogenous view of the cache hierarchy. That in get_cacheinfo()
33 * happens to be the case for the current set of RISC-V systems, but in get_cacheinfo()
42 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo()
43 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo()
44 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo()
51 uintptr_t get_cache_size(u32 level, enum cache_type type) in get_cache_size() argument
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | p4080si-pre.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache {
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|
| /kernel/linux/linux-5.10/drivers/acpi/ |
| D | pptt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pptt.c - parsing of Processor Properties Topology Table (PPTT)
8 * which is optionally used to describe the processor and cache topology.
14 * the caches available at that level. Each cache structure optionally
15 * contains properties describing the cache at a given level which can be
33 if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) in fetch_pptt_subtable()
38 if (entry->length == 0) in fetch_pptt_subtable()
41 if (pptt_ref + entry->length > table_hdr->length) in fetch_pptt_subtable()
65 if (resource >= node->number_of_priv_resources) in acpi_get_pptt_resource()
81 * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
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|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page …
18 "BriefDescription": "L1 data cache refill"
21 …tion": "L1 data cache access. This event counts any load or store operation or page table walk acc…
24 "BriefDescription": "L1 data cache access"
33 …Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instructi…
36 "BriefDescription": "L1 instruction cache access"
39 …cache Write-Back. This event counts any write-back of data from the L1 data cache to L2 or L3. Thi…
42 "BriefDescription": "L1 data cache Write-Back"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/mm/ |
| D | numaperf.rst | 9 as CPU cache coherence, but may have different performance. For example,
20 +------------------+ +------------------+
21 | Compute Node 0 +-----+ Compute Node 1 |
23 +--------+---------+ +--------+---------+
25 +--------+---------+ +--------+---------+
27 +------------------+ +--------+---------+
35 performance when accessing a given memory target. Each initiator-target
47 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
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|
| /kernel/linux/linux-5.10/arch/s390/kernel/ |
| D | cache.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Extract CPU cache information and expose them via sysfs.
71 struct cacheinfo *cache; in show_cacheinfo() local
77 for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) { in show_cacheinfo()
78 cache = this_cpu_ci->info_list + idx; in show_cacheinfo()
79 seq_printf(m, "cache%-11d: ", idx); in show_cacheinfo()
80 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
81 seq_printf(m, "type=%s ", cache_type_string[cache->type]); in show_cacheinfo()
83 cache->disable_sysfs ? "Shared" : "Private"); in show_cacheinfo()
84 seq_printf(m, "size=%dK ", cache->size >> 10); in show_cacheinfo()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 1 * Andestech L2 cache Controller
3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
10 representation of an Andestech L2 cache controller.
13 - compatible:
17 - reg : Physical base address and size of cache controller's memory mapped
18 - cache-unified : Specifies the cache is a unified cache.
19 - cache-level : Should be set to 2 for a level 2 cache.
23 cache-controller@e0500000 {
26 cache-unified;
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| /kernel/linux/linux-5.10/include/linux/ |
| D | cacheinfo.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 * struct cacheinfo - represent a cache leaf node
25 * @id: This cache's id. It is unique among caches with the same (type, level).
26 * @type: type of the cache - data, inst or unified
27 * @level: represents the hierarchy in the multi-level cache
28 * @coherency_line_size: size of each cache line usually representing
30 * @number_of_sets: total number of sets, a set is a collection of cache
33 * block can be placed in the cache
34 * @physical_line_partition: number of physical cache lines sharing the
36 * @size: Total size of the cache
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Socionext Inc.
15 #include <asm/hardware/cache-uniphier.h>
21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
24 #define UNIPHIER_SSCC_ON BIT(0) /* enable cache */
32 #define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
38 #define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
46 #define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */
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|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
[all …]
|
| /kernel/linux/linux-5.10/security/selinux/ss/ |
| D | sidtab.c | 1 // SPDX-License-Identifier: GPL-2.0
31 #define sid_to_index(sid) (sid - (SECINITSID_NUM + 1))
37 memset(s->roots, 0, sizeof(s->roots)); in sidtab_init()
40 s->isids[i].set = 0; in sidtab_init()
42 s->frozen = false; in sidtab_init()
43 s->count = 0; in sidtab_init()
44 s->convert = NULL; in sidtab_init()
45 hash_init(s->context_to_sid); in sidtab_init()
47 spin_lock_init(&s->lock); in sidtab_init()
50 s->cache_free_slots = CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE; in sidtab_init()
[all …]
|