| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 3 * Processor cache information made available to userspace via sysfs;
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
53 /* Allow for both [di]-cache-line-size and
54 * [di]-cache-block-size properties. According to the PowerPC
[all …]
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| /kernel/linux/linux-5.10/drivers/md/ |
| D | dm-cache-target.c | 10 #include "dm-cache-metadata.h"
22 #define DM_MSG_PREFIX "cache"
25 "A percentage of time allocated for copying to and/or from cache");
33 * cblock: index of a cache block
34 * promotion: movement of a block from origin to cache
35 * demotion: movement of a block from cache to origin
36 * migration: movement of a block between the origin and cache device,
310 * The block size of the device holding cache data must be
325 * dirty. If you lose the cache device you will lose data.
331 * Data is written to both cache and origin. Blocks are never
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| /kernel/linux/linux-5.10/fs/cachefiles/ |
| D | bind.c | 2 /* Bind and unbind a cache from the filesystem backing it
25 * bind a directory as a cache
27 int cachefiles_daemon_bind(struct cachefiles_cache *cache, char *args) in cachefiles_daemon_bind() argument
30 cache->frun_percent, in cachefiles_daemon_bind()
31 cache->fcull_percent, in cachefiles_daemon_bind()
32 cache->fstop_percent, in cachefiles_daemon_bind()
33 cache->brun_percent, in cachefiles_daemon_bind()
34 cache->bcull_percent, in cachefiles_daemon_bind()
35 cache->bstop_percent, in cachefiles_daemon_bind()
39 ASSERT(cache->fstop_percent >= 0 && in cachefiles_daemon_bind()
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| D | daemon.c | 59 int (*handler)(struct cachefiles_cache *cache, char *args);
85 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
97 /* allocate a cache record */ in cachefiles_daemon_open()
98 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
99 if (!cache) { in cachefiles_daemon_open()
104 mutex_init(&cache->daemon_mutex); in cachefiles_daemon_open()
105 cache->active_nodes = RB_ROOT; in cachefiles_daemon_open()
106 rwlock_init(&cache->active_lock); in cachefiles_daemon_open()
107 init_waitqueue_head(&cache->daemon_pollwq); in cachefiles_daemon_open()
114 cache->frun_percent = 7; in cachefiles_daemon_open()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
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| /kernel/linux/linux-5.10/fs/fscache/ |
| D | cache.c | 2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
21 * look up a cache tag
67 * release a reference to a cache tag
86 * select a cache in which to store an object
87 * - the cache addremove semaphore must be at least read-locked by the caller
95 struct fscache_cache *cache; in fscache_select_cache_for_object() local
100 _leave(" = NULL [no cache]"); in fscache_select_cache_for_object()
104 /* we check the parent to determine the cache to use */ in fscache_select_cache_for_object()
108 * cache */ in fscache_select_cache_for_object()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
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| /kernel/linux/linux-5.10/fs/ |
| D | mbcache.c | 16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
50 static inline struct hlist_bl_head *mb_cache_entry_head(struct mb_cache *cache, in mb_cache_entry_head() argument
53 return &cache->c_hash[hash_32(key, cache->c_bucket_bits)]; in mb_cache_entry_head()
58 * in cache
63 * mb_cache_entry_create - create entry in cache
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| /kernel/linux/linux-5.10/fs/squashfs/ |
| D | cache.c | 8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
49 * Look-up block in cache, and increment usage count. If not in cache, read
53 struct squashfs_cache *cache, u64 block, int length) in squashfs_cache_get() argument
58 spin_lock(&cache->lock); in squashfs_cache_get()
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| /kernel/linux/linux-5.10/mm/ |
| D | swap_slots.c | 3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
42 /* Serialize swap slots cache enable/disable operations */
107 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
116 struct swap_slots_cache *cache; in alloc_swap_slot_cache() local
137 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
138 if (cache->slots || cache->slots_ret) { in alloc_swap_slot_cache()
139 /* cache already allocated */ in alloc_swap_slot_cache()
148 if (!cache->lock_initialized) { in alloc_swap_slot_cache()
149 mutex_init(&cache->alloc_lock); in alloc_swap_slot_cache()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
19 const: socionext,uniphier-system-cache
30 Interrupts can be used to notify the completion of cache operations.
36 cache-unified: true
38 cache-size: true
40 cache-sets: true
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| /kernel/linux/linux-5.10/fs/nfs/ |
| D | nfs42xattr.c | 6 * User extended attribute client side cache functions.
21 * a cache structure attached to NFS inodes. This structure is allocated
22 * when needed, and freed when the cache is zapped.
24 * The cache structure contains as hash table of entries, and a pointer
25 * to a special-cased entry for the listxattr cache.
28 * counting. The cache entries use a similar refcounting scheme.
30 * This makes freeing a cache, both from the shrinker and from the
31 * zap cache path, easy. It also means that, in current use cases,
40 * Two shrinkers deal with the cache entries themselves: one for
45 * The other shrinker frees the cache structures themselves.
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
126 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
133 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
140 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
147 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an …
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
43 i-cache-sets = <256>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
46 d-cache-sets = <128>;
47 next-level-cache = <&L2_0>;
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
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| /kernel/linux/linux-5.10/drivers/acpi/acpica/ |
| D | utcache.c | 4 * Module Name: utcache - local cache allocation routines
21 * PARAMETERS: cache_name - Ascii name for the cache
23 * max_depth - Maximum depth of the cache (in objects)
24 * return_cache - Where the new cache object is returned
28 * DESCRIPTION: Create a cache object
36 struct acpi_memory_list *cache; in acpi_os_create_cache() local
44 /* Create the cache object */ in acpi_os_create_cache()
46 cache = acpi_os_allocate(sizeof(struct acpi_memory_list)); in acpi_os_create_cache()
47 if (!cache) { in acpi_os_create_cache()
51 /* Populate the cache object and return it */ in acpi_os_create_cache()
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …n into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
56 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l…
[all …]
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| /kernel/linux/linux-5.10/fs/btrfs/tests/ |
| D | free-space-tree-tests.c | 21 struct btrfs_block_group *cache, in __check_free_space_extents() argument
34 info = search_free_space_info(trans, cache, path, 0); in __check_free_space_extents()
51 end = cache->start + cache->length; in __check_free_space_extents()
59 bit = free_space_test_bit(cache, path, offset); in __check_free_space_extents()
108 struct btrfs_block_group *cache, in check_free_space_extents() argument
117 info = search_free_space_info(trans, cache, path, 0); in check_free_space_extents()
126 ret = __check_free_space_extents(trans, fs_info, cache, path, extents, in check_free_space_extents()
133 ret = convert_free_space_to_extents(trans, cache, path); in check_free_space_extents()
139 ret = convert_free_space_to_bitmaps(trans, cache, path); in check_free_space_extents()
145 return __check_free_space_extents(trans, fs_info, cache, path, extents, in check_free_space_extents()
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| D | free-space-tests.c | 10 #include "../free-space-cache.h"
20 static int test_extents(struct btrfs_block_group *cache) in test_extents() argument
27 ret = btrfs_add_free_space(cache, 0, SZ_4M); in test_extents()
33 ret = btrfs_remove_free_space(cache, 0, SZ_4M); in test_extents()
39 if (test_check_exists(cache, 0, SZ_4M)) { in test_extents()
45 ret = btrfs_add_free_space(cache, 0, SZ_4M); in test_extents()
51 ret = btrfs_remove_free_space(cache, 3 * SZ_1M, SZ_1M); in test_extents()
57 ret = btrfs_remove_free_space(cache, 0, SZ_1M); in test_extents()
63 ret = btrfs_remove_free_space(cache, SZ_2M, 4096); in test_extents()
69 if (test_check_exists(cache, 0, SZ_1M)) { in test_extents()
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| /kernel/linux/linux-5.10/Documentation/filesystems/caching/ |
| D | backend-api.rst | 4 FS-Cache Cache backend API
7 The FS-Cache system provides an API by which actual caches can be supplied to
8 FS-Cache for it to then serve out to network filesystems and other interested
11 This API is declared in <linux/fscache-cache.h>.
14 Initialising and Registering a Cache
17 To start off, a cache definition must be initialised and registered for each
18 cache the backend wants to make available. For instance, CacheFS does this in
21 The cache definition (struct fscache_cache) should be initialised by calling::
23 void fscache_init_cache(struct fscache_cache *cache,
30 * "cache" is a pointer to the cache definition;
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …n into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
56 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l…
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
27 i-cache-sets = <256>;
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 next-level-cache = <&l2_0>;
40 i-cache-size = <0xc000>;
41 i-cache-line-size = <64>;
42 i-cache-sets = <256>;
[all …]
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| D | armada-ap807-quad.dtsi | 25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
27 i-cache-sets = <256>;
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 next-level-cache = <&l2_0>;
40 i-cache-size = <0xc000>;
41 i-cache-line-size = <64>;
42 i-cache-sets = <256>;
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | extended.json | 21 …ory write to the Level-1 Data cache directory where the returned cache line was sourced from the L…
28 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
35 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …to the Level-1 Data cache where the installed cache line was sourced from memory that is attached …
56 …el-1 Instruction cache where the installed cache line was sourced from memory that is attached to …
63 …-Cache where the line was originally in a Read-Only state in the cache but has been updated to be …
105 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
112 …y write to the Level-1 Data cache directory where the returned cache line was sourced from an Off …
119 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an …
126 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
50 "BriefDescription": "L1 Cache evictions for dirty data"
54 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
86 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
92 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
98 …iption": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | extended.json | 7 …"A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from…
14 …"A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from…
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
42 …irectory write to the Level-1 D-Cache directory where the returned cache line was sourced from an …
49 …directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an…
56 …directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an…
63 …-Cache where the line was originally in a Read-Only state in the cache but has been updated to be …
70 …irectory write to the Level-1 D-Cache directory where the returned cache line was sourced from an …
77 …irectory write to the Level-1 I-Cache directory where the returned cache line was sourced from an …
91 …te to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached …
[all …]
|