| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | mt6358-regulator.txt | 34 regulator-ramp-delay = <12500>;
35 regulator-enable-ramp-delay = <0>;
43 regulator-ramp-delay = <6250>;
44 regulator-enable-ramp-delay = <200>;
52 regulator-ramp-delay = <50000>;
53 regulator-enable-ramp-delay = <250>;
60 regulator-ramp-delay = <6250>;
61 regulator-enable-ramp-delay = <200>;
69 regulator-ramp-delay = <6250>;
70 regulator-enable-ramp-delay = <200>;
[all …]
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| D | mt6397-regulator.txt | 34 regulator-ramp-delay = <12500>;
35 regulator-enable-ramp-delay = <200>;
43 regulator-ramp-delay = <12500>;
44 regulator-enable-ramp-delay = <115>;
52 regulator-ramp-delay = <12500>;
53 regulator-enable-ramp-delay = <115>;
62 regulator-ramp-delay = <12500>;
63 regulator-enable-ramp-delay = <115>;
72 regulator-ramp-delay = <12500>;
73 regulator-enable-ramp-delay = <115>;
[all …]
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| D | mt6323-regulator.txt | 27 regulator-ramp-delay = <12500>;
36 regulator-ramp-delay = <25000>;
51 regulator-enable-ramp-delay = <90>;
60 regulator-enable-ramp-delay = <185>;
67 regulator-enable-ramp-delay = <185>;
74 regulator-enable-ramp-delay = <185>;
81 regulator-enable-ramp-delay = <216>;
90 regulator-enable-ramp-delay = <216>;
97 regulator-enable-ramp-delay = <216>;
106 regulator-enable-ramp-delay = <216>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6358.dtsi | 25 regulator-ramp-delay = <12500>;
26 regulator-enable-ramp-delay = <0>;
35 regulator-ramp-delay = <6250>;
36 regulator-enable-ramp-delay = <200>;
45 regulator-ramp-delay = <50000>;
46 regulator-enable-ramp-delay = <250>;
54 regulator-ramp-delay = <6250>;
55 regulator-enable-ramp-delay = <200>;
64 regulator-ramp-delay = <6250>;
65 regulator-enable-ramp-delay = <200>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 26 PHY DLL delays are used to delay the data valid window, and align the window
29 write line delay value, clock read command line delay value, clock read data
30 positive edge delay value and clock read data negative edge delay value.
31 Each cell's delay value unit is cycle of the PHY clock.
33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
[all …]
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| D | cdns,sdhci.yaml | 33 # They are used to delay the data valid window, and align the window to
34 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37 cdns,phy-input-delay-sd-highspeed:
38 description: Value of the delay in the input path for SD high-speed timing
43 cdns,phy-input-delay-legacy:
44 description: Value of the delay in the input path for legacy timing
49 cdns,phy-input-delay-sd-uhs-sdr12:
50 description: Value of the delay in the input path for SD UHS SDR12 timing
55 cdns,phy-input-delay-sd-uhs-sdr25:
56 description: Value of the delay in the input path for SD UHS SDR25 timing
[all …]
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| D | sdhci-am654.yaml | 47 # Used to delay the data valid window and align it to the sampling clock.
52 description: Output tap delay for SD/MMC legacy timing
58 description: Output tap delay for MMC high speed timing
64 description: Output tap delay for SD high speed timing
70 description: Output tap delay for SD UHS SDR12 timing
76 description: Output tap delay for SD UHS SDR25 timing
82 description: Output tap delay for SD UHS SDR50 timing
88 description: Output tap delay for SD UHS SDR104 timing
94 description: Output tap delay for SD UHS DDR50 timing
100 description: Output tap delay for eMMC DDR52 timing
[all …]
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| D | fsl-imx-esdhc.yaml | 56 fsl,delay-line:
59 Specify the number of delay cells for override mode.
60 This is used to set the clock delay for DLL(Delay Line) on override mode
63 chapter, DLL (Delay Line) section in RM for details.
82 Specify the start delay cell point when send first CMD19 in tuning procedure.
88 Specify the increasing delay cell steps in tuning procedure.
89 The uSDHC use one delay cell as default increasing step to do tuning process.
90 This property allows user to change the tuning step to more than one delay
92 tuning step can't find the proper delay window within limited tuning retries.
95 fsl,strobe-dll-delay-target:
[all …]
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| /kernel/linux/linux-5.10/tools/time/ |
| D | udelay_test.sh | 24 delay=$1
25 echo $delay > $UDELAY_PATH
40 # Delay for a variety of times.
42 for (( delay = 1; delay < 200; delay += 1 )); do
43 test_one $delay
45 for (( delay = 200; delay < 500; delay += 10 )); do
46 test_one $delay
48 for (( delay = 500; delay <= 2000; delay += 100 )); do
49 test_one $delay
55 echo "ERROR: $count delays failed to delay long enough"
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos7-espresso.dts | 86 samsung,i2c-sda-delay = <100>;
112 regulator-enable-ramp-delay = <125>;
120 regulator-enable-ramp-delay = <125>;
129 regulator-enable-ramp-delay = <125>;
137 regulator-enable-ramp-delay = <125>;
145 regulator-enable-ramp-delay = <125>;
152 regulator-enable-ramp-delay = <125>;
159 regulator-enable-ramp-delay = <125>;
167 regulator-enable-ramp-delay = <125>;
174 regulator-enable-ramp-delay = <125>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/ |
| D | sc2731.dtsi | 123 regulator-ramp-delay = <25000>;
131 regulator-ramp-delay = <25000>;
139 regulator-ramp-delay = <25000>;
140 regulator-enable-ramp-delay = <100>;
148 regulator-enable-ramp-delay = <100>;
155 regulator-enable-ramp-delay = <100>;
156 regulator-ramp-delay = <25000>;
163 regulator-enable-ramp-delay = <100>;
164 regulator-ramp-delay = <25000>;
171 regulator-enable-ramp-delay = <100>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/accounting/ |
| D | delay-accounting.rst | 2 Delay accounting
9 The per-task delay accounting functionality measures
25 delay statistics aggregated for all tasks (or threads) belonging to a
30 aggregate delay statistics into arbitrary groups. To enable this, delay
38 Delay accounting uses the taskstats interface which is described
41 statistics. The delay accounting functionality populates specific fields of
46 for a description of the fields pertaining to delay accounting.
48 delay seen for cpu, sync block I/O, swapin, memory reclaim etc.
51 counter (say cpu_delay_total) for a task will give the delay
61 commands to be run and the corresponding delay statistics to be displayed. It
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 14 reset. After a delay specified by active-delay, the GPIO is set to
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
40 - active-delay: Delay (default 100) to wait after driving gpio active [ms]
41 - inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms]
42 - wait-delay: Delay (default 3000) to wait after completing restart
51 active-delay = <100>;
52 inactive-delay = <100>;
53 wait-delay = <3000>;
|
| /kernel/linux/linux-5.10/drivers/input/touchscreen/ |
| D | wm9705.c | 16 #include <linux/delay.h>
52 * Set adc sample delay.
58 * This delay can be set by setting delay = n, where n is the array
59 * position of the delay in the array delay_table below.
63 static int delay = 4; variable
64 module_param(delay, int, 0);
65 MODULE_PARM_DESC(delay, "Set adc sample delay.");
86 * order to minimise this, a signal may be applied to the MASK pin to delay or
89 * 0 = No delay or sync
91 * 2 = Edge triggered, edge on pin delays conversion by delay param (above)
[all …]
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| D | wm9712.c | 16 #include <linux/delay.h>
65 * Set adc sample delay.
71 * This delay can be set by setting delay = n, where n is the array
72 * position of the delay in the array delay_table below.
76 static int delay = 3; variable
77 module_param(delay, int, 0);
78 MODULE_PARM_DESC(delay, "Set adc sample delay.");
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
97 * 0 = No delay or sync
99 * 2 = Edge triggered, edge on pin delays conversion by delay param (above)
[all …]
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| D | wm9713.c | 16 #include <linux/delay.h>
65 * Set adc sample delay.
71 * This delay can be set by setting delay = n, where n is the array
72 * position of the delay in the array delay_table below.
76 static int delay = 4; variable
77 module_param(delay, int, 0);
78 MODULE_PARM_DESC(delay, "Set adc sample delay.");
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
97 * 0 = No delay or sync
99 * 2 = Edge triggered, edge on pin delays conversion by delay param (above)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | mt6323.dtsi | 31 regulator-ramp-delay = <12500>;
40 regulator-ramp-delay = <25000>;
55 regulator-enable-ramp-delay = <90>;
64 regulator-enable-ramp-delay = <185>;
71 regulator-enable-ramp-delay = <185>;
78 regulator-enable-ramp-delay = <185>;
85 regulator-enable-ramp-delay = <216>;
94 regulator-enable-ramp-delay = <216>;
101 regulator-enable-ramp-delay = <216>;
110 regulator-enable-ramp-delay = <216>;
[all …]
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| D | mt8135-evbp1.dts | 32 regulator-ramp-delay = <12500>;
40 regulator-ramp-delay = <12500>;
48 regulator-ramp-delay = <12500>;
56 regulator-ramp-delay = <12500>;
64 regulator-ramp-delay = <12500>;
72 regulator-ramp-delay = <12500>;
73 regulator-enable-ramp-delay = <115>;
80 regulator-ramp-delay = <12500>;
88 regulator-ramp-delay = <12500>;
106 regulator-enable-ramp-delay = <218>;
[all …]
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| D | motorola-cpcap-mapphone.dtsi | 158 regulator-enable-ramp-delay = <50000>;
165 regulator-enable-ramp-delay = <1000>;
172 regulator-enable-ramp-delay = <1000>;
179 regulator-enable-ramp-delay = <1000>;
185 regulator-enable-ramp-delay = <1000>;
191 regulator-enable-ramp-delay = <1000>;
197 regulator-enable-ramp-delay = <1000>;
205 regulator-enable-ramp-delay = <1000>;
211 regulator-enable-ramp-delay = <100>;
217 regulator-enable-ramp-delay = <1000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra210-p2180.dtsi | 115 regulator-enable-ramp-delay = <146>;
116 regulator-ramp-delay = <27500>;
126 regulator-enable-ramp-delay = <130>;
127 regulator-ramp-delay = <27500>;
137 regulator-enable-ramp-delay = <176>;
138 regulator-ramp-delay = <27500>;
150 regulator-enable-ramp-delay = <242>;
151 regulator-ramp-delay = <27500>;
163 regulator-enable-ramp-delay = <26>;
164 regulator-ramp-delay = <100000>;
[all …]
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| D | tegra210-p3450-0000.dts | 268 regulator-enable-ramp-delay = <146>;
269 regulator-disable-ramp-delay = <4080>;
270 regulator-ramp-delay = <27500>;
271 regulator-ramp-delay-scale = <300>;
284 regulator-enable-ramp-delay = <176>;
285 regulator-disable-ramp-delay = <145800>;
286 regulator-ramp-delay = <27500>;
287 regulator-ramp-delay-scale = <300>;
300 regulator-enable-ramp-delay = <176>;
301 regulator-disable-ramp-delay = <32000>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 67 - mpmc,write-enable-delay: Delay from chip select assertion to write
70 - mpmc,output-enable-delay: Delay from chip select assertion to output
73 - mpmc,write-access-delay: Delay from chip select assertion to write
76 - mpmc,read-access-delay: Delay from chip select assertion to read
79 - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
82 - mpmc,turn-round-delay: Delay between access to memory banks in nano
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
112 mpmc,read-enable-delay = <70>;
113 mpmc,page-mode-read-delay = <70>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | brcm,sr-thermal.txt | 11 - polling-delay: Max number of milliseconds to wait between polls.
34 polling-delay-passive = <0>;
35 polling-delay = <1000>;
46 polling-delay-passive = <0>;
47 polling-delay = <1000>;
58 polling-delay-passive = <0>;
59 polling-delay = <1000>;
70 polling-delay-passive = <0>;
71 polling-delay = <1000>;
82 polling-delay-passive = <0>;
[all …]
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| /kernel/linux/linux-5.10/include/soc/at91/ |
| D | at91sam9_ddrsdr.h | 51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
62 #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
39 ti,c64x+pll-lock-delay = <80000>;
|