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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/
D	cache.json	5 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 6 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 11 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 12 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 17 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", 18 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only dema… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …sor's data cache was reloaded from a location other than the local core's L2 due to a demand load", 36 …r's data cache was reloaded from a location other than the local core's L2 due to either only dema… [all …]
D	frontend.json	89 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 90 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 95 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 96 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 101 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction f… 102 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instru… 107 …as reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction f… 108 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either an instru… 113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an… 114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e… [all …]
D	marked.json	35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", 65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", 71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", 77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 95 …"Duration in cycles to reload from a location other than the local core's L2 due to a marked load", [all …]
D	other.json	77 …"BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interl… 95 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Tar… 101 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the BHT Direction P… 107 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Targ… 113 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address … 251 "BriefDescription": "Completion stall due to IFU", 257 "BriefDescription": "Completion stall due to CO q full", 263 "BriefDescription": "completion stall due to flush by own thread", 269 "BriefDescription": "Completion stall due to mem ECC delay", 275 "BriefDescription": "Completion stall due to nop", [all …]
D	translation.json	29 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 35 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …try was loaded into the TLB from a location other than the local core's L2 due to a data side requ… 53 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side requ… 59 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requ… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side requ… 77 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side requ… 83 … Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side requ… [all …]
D	pipeline.json	29 "BriefDescription": "Completion stall due to a Branch Unit", 53 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 54 …"PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict" 59 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 65 "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 66 "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory" 77 "BriefDescription": "Completion stall due to LSU reject ERAT miss", 83 "BriefDescription": "Completion stall due to a long latency fixed point instruction", 89 "BriefDescription": "Completion stall due to FXU", 95 "BriefDescription": "completion stall due to hwsync", [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
D	translation.json	15 …che was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load" 25 …nto the TLB from another chip's memory on the same Node or Group (Distant) due to a data side requ… 35 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction si… 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 60 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load" 75 … either shared or modified data from another core's L2/L3 on the same chip due to a instruction si… 80 … was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction f… 95 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load" [all …]
D	marked.json	20 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requ… 25 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load" 35 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction f… 55 "BriefDescription": "Completion stall due to ntc flush" 60 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data si… 70 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data si… 80 …sor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction f… 85 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe… 95 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data si… 100 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requ… [all …]
D	pipeline.json	30 …ded either shared or modified data from another core's L2/L3 on the same chip due to a marked load" 35 …into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data si… 40 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requ… 80 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data si… 90 …he was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load" 95 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a data side requ… 115 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data si… 145 …"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from beyond … 150 "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch" 155 "BriefDescription": "Ict empty for this thread due to Icache Miss" [all …]
D	frontend.json	5 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction si… 15 …try was loaded into the TLB from a location other than the local core's L3 due to a instruction si… 50 …s reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load" 55 …The processor's data cache was reloaded from local core's L3 without conflict due to a demand load" 95 …as reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load" 110 "BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)" 115 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction si… 150 …ocessor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load" 155 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load" 170 …oad either shared or modified data from another core's L2/L3 on the same chip due to a marked load" [all …]
D	cache.json	15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 25 …n cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" 40 … either shared or modified data from another core's L2/L3 on the same chip due to an instruction f… 50 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction f… 55 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f… 70 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data si… 80 …nto the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data si… 85 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 100 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f…
D	other.json	40 "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue" 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 50 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side requ… 55 …A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Directio… 95 …he processor's Instruction cache was reloaded from the local chip's Memory due to an instruction f… 145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load" 180 "BriefDescription": "Dispatch Hold: Due to TLBIE" 205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" 225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load" 230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load" [all …]
D	pmc.json	20 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data si… 30 …try was loaded into the TLB from a location other than the local core's L3 due to a data side requ… 40 …try was loaded into the TLB from a location other than the local core's L2 due to a marked data si… 45 "BriefDescription": "Completion stall due to a Branch Unit" 55 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 70 …"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked loa… 90 …o the TLB from a memory location including L4 from local remote or distant due to a data side requ… 95 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data si… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a mark… 110 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side requ…
D	memory.json	20 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load" 30 "BriefDescription": "DERAT Reloaded due to a DERAT miss" 35 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load" 50 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand … 65 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction f… 80 …ocessor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load" 85 "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)" 100 …The processor's data cache was reloaded from local core's L2 without conflict due to a demand load" 105 …as reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
D	virtual-memory.json	4 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 12 "BriefDescription": "Page walk completed due to a demand load to a 4K page" 16 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 24 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page" 28 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 36 "BriefDescription": "Page walk completed due to a demand load to a 1GB page" 40 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat… 48 "BriefDescription": "Page walks outstanding due to a demand load every cycle." 52 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 60 "BriefDescription": "Page walk completed due to a demand data store to a 4K page" [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/
D	other.json	28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 82 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/tremontx/
D	virtual-memory.json	4 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 12 "BriefDescription": "Page walk completed due to a demand load to a 4K page." 16 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 24 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page." 28 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 36 "BriefDescription": "Page walk completed due to a demand data store to a 4K page." 40 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 48 "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page." 64 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla… 72 "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page." [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/
D	memory.json	11 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on … 15 …ly counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity … 22 …"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation … 26 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/co… 33 …"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE pref… 37 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock … 44 …"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElis… 48 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit b… 55 …"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock n… 59 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an un… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/
D	other.json	17 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 23 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 29 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 35 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 41 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 47 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 53 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t…
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/
D	memory.json	35 …"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a … 38 …"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a… 45 …"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store t… 48 …"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store … 55 …"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not e… 58 …"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not … 65 …"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and … 68 …"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and… 75 …"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported al… 78 …"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported a… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/silvermont/
D	other.json	`3 … stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but … 9 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss." 12 …ed due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is un… 18 "BriefDescription": "Cycles code-fetch stalled due to any reason."`
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswellx/
D	floating-point.json	35 "BriefDescription": "Number of X87 assists due to output value.", 38 "PublicDescription": "Number of X87 FP assists due to output values.", 45 "BriefDescription": "Number of X87 assists due to input value.", 48 "PublicDescription": "Number of X87 FP assists due to input values.", 55 "BriefDescription": "Number of SIMD FP assists due to Output values", 58 "PublicDescription": "Number of SIMD FP assists due to output values.", 65 "BriefDescription": "Number of SIMD FP assists due to input values", 68 "PublicDescription": "Number of SIMD FP assists due to input values.",
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/
D	jkt-metrics.json	7 …ivered no uops while Backend could have accepted them. For example; stalls due to instruction-cach… 14 …ivered no uops while Backend could have accepted them. For example; stalls due to instruction-cach… 17 …"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculatio… 21 …due to incorrect speculations. This include slots used to issue uops that do not eventually get re… 24 …"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculatio… 28 …due to incorrect speculations. This include slots used to issue uops that do not eventually get re… 31 …is category represents fraction of slots where no uops are being delivered due to a lack of requir… 35 …due to a lack of required resources for accepting new uops in the Backend. Backend is the portion … 38 …is category represents fraction of slots where no uops are being delivered due to a lack of requir… 42 …due to a lack of required resources for accepting new uops in the Backend. Backend is the portion …
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/
D	snb-metrics.json	7 …ivered no uops while Backend could have accepted them. For example; stalls due to instruction-cach… 14 …ivered no uops while Backend could have accepted them. For example; stalls due to instruction-cach… 17 …"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculatio… 21 …due to incorrect speculations. This include slots used to issue uops that do not eventually get re… 24 …"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculatio… 28 …due to incorrect speculations. This include slots used to issue uops that do not eventually get re… 31 …is category represents fraction of slots where no uops are being delivered due to a lack of requir… 35 …due to a lack of required resources for accepting new uops in the Backend. Backend is the portion … 38 …is category represents fraction of slots where no uops are being delivered due to a lack of requir… 42 …due to a lack of required resources for accepting new uops in the Backend. Backend is the portion …
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/
D	other.json	`4 …ed due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is un… 10 "BriefDescription": "Cycles code-fetch stalled due to any reason." 14 … stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but … 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss." 24 …cle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_…`

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