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Searched +full:emc +full:- +full:timings +full:- +full:3 (Results 1 – 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
55 #define EMC1_EMC_DATA_BRLSHFT_0_INDEX 3
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
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Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
169 #define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3
204 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
224 [3] = EMC_RP,
336 struct emc_timing *timings; member
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
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Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
82 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
151 struct emc_timing *timings; member
163 struct tegra_emc *emc = data; in tegra_emc_isr() local
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
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Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
197 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
262 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
284 DRAM_TYPE_DDR2 = 3
476 struct emc_timing *timings; member
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
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Dtegra210-emc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
144 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3)
191 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN BIT(3)
264 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
290 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
673 #define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR BIT(3)
675 #define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR BIT(3)
884 #define DRAM_TYPE_DDR2 3
891 /* nominal EMC frequency table */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
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Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
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/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
24 #include <soc/tegra/emc.h>
46 * List of clock sources for various parents the EMC clock can have.
55 #define EMC_SRC_CLK_M 3
78 struct tegra_emc *emc; member
81 struct emc_timing *timings; member
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
109 * safer since things have EMC rate floors. Also don't touch parent_rate
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Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
25 #define CLK_SRC_CLK_M 3
53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
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