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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
15 compatible = "renesas,r8a7795";
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
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/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
124 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
125 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
126 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
127 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
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Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
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Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
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Dr8a77965-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
17 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
135 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
136 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
137 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
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Dr8a7796-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
6 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
9 * Based on r8a7795-cpg-mssr.c
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
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Dr8a774e1-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
124 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
142 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
143 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
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/kernel/linux/linux-5.10/drivers/net/ethernet/renesas/
Dravb_main.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
14 #include <linux/dma-mapping.h>
68 return -ETIMEDOUT; in ravb_wait()
89 switch (priv->speed) { in ravb_set_rate()
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); in ravb_set_buffer_align()
104 skb_reserve(skb, RAVB_ALIGN - reserve); in ravb_set_buffer_align()
115 ether_addr_copy(ndev->dev_addr, mac); in ravb_read_mac_address()
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; in ravb_read_mac_address()
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/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
Dpfc-r8a7796.c1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 * R-Car Gen3 processor support - PFC hardware block.
259 … /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 … /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 … /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 … /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 … /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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