| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
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| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
46 const: arm,psci-0.2
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
28 const: domain-idle-state
30 entry-latency-us:
32 The worst case latency in microseconds required to enter the idle
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| D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
24 \#power-domain-cells property in the PM domain provider node.
28 pattern: "^(power-controller|power-domain)([@-].*)?$"
30 domain-idle-states:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | dt_idle_states.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "DT idle-states: " fmt
33 idle_state->enter = match_id->data; in init_state_node()
39 idle_state->enter_s2idle = match_id->data; in init_state_node()
41 err = of_property_read_u32(state_node, "wakeup-latency-us", in init_state_node()
42 &idle_state->exit_latency); in init_state_node()
46 err = of_property_read_u32(state_node, "entry-latency-us", in init_state_node()
49 pr_debug(" * %pOF missing entry-latency-us property\n", in init_state_node()
51 return -EINVAL; in init_state_node()
54 err = of_property_read_u32(state_node, "exit-latency-us", in init_state_node()
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| D | cpuidle-pseries.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * cpuidle-pseries - idle state cpuidle driver.
78 * were soft-disabled in check_and_cede_processor()
92 * "ibm,get-systems-parameter" RTAS call with the token
98 * table with all the parameters to ibm,get-system-parameters.
99 * CEDE_LATENCY_TOKEN corresponds to the token value for Cede Latency
105 * If the platform supports the cede latency settings information system
109 * a. The first byte is the length “N” of each cede latency setting record minus
112 * b. For each supported cede latency setting a cede latency setting record
115 * -----------------------------
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm630.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
31 state. Retention may have a slightly higher latency than Standby.
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
52 power modes possible at this state is vast, the exit latency and the residency
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
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| /kernel/linux/linux-5.10/tools/testing/selftests/ftrace/test.d/preemptirq/ |
| D | irqsoff_tracer.tc | 2 # SPDX-License-Identifier: GPL-2.0
46 grep -q "tracer: preemptoff" trace || fail
49 egrep -q "5.....us : <stack trace>" trace || fail
51 # Check for 500ms of latency
52 egrep -q "latency: 5..... us" trace || fail
69 grep -q "tracer: irqsoff" trace || fail
72 egrep -q "5.....us : <stack trace>" trace || fail
74 # Check for 500ms of latency
75 egrep -q "latency: 5..... us" trace || fail
78 exit 0
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| /kernel/linux/linux-5.10/drivers/cpuidle/governors/ |
| D | menu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * menu.c - the menu idle governor
5 * Copyright (C) 2006-2007 Adam Belay <abelay@novell.com>
36 * 3) Latency tolerance (from pmqos infrastructure)
40 * -----------------------
41 * C state entry and exit have an energy cost, and a certain amount of time in
43 * provides us this duration in the "target_residency" field. So all that we
68 * Repeatable-interval-detector
69 * ----------------------------
79 * ---------------------------
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| /kernel/linux/linux-5.10/Documentation/trace/ |
| D | ftrace.rst | 2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
28 There's latency tracing to examine what occurs between interrupts
41 ----------------------
43 See :doc:`ftrace-design` for details for arch porters and such.
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hi3660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
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| /kernel/linux/linux-5.10/drivers/pci/pcie/ |
| D | aspm.c | 1 // SPDX-License-Identifier: GPL-2.0
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
69 /* Exit latencies */
70 struct aspm_latency latency_up; /* Upstream direction exit latency */
71 struct aspm_latency latency_dw; /* Downstream direction exit latency */
121 return link->aspm_default; in policy_to_aspm_state()
137 return link->clkpm_default; in policy_to_clkpm_state()
145 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | cs4234.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 // cs4234.c -- ALSA SoC CS4234 driver
44 /* -89.92dB to +6.02dB with step of 0.38dB */
45 static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0);
48 "0us", "100us", "150us", "200us", "225us", "250us", "275us", "300us",
49 "325us", "350us", "375us", "400us", "425us", "450us", "475us", "500us",
96 regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val); in cs4234_dac14_grp_delay_put()
98 ret = -EBUSY; in cs4234_dac14_grp_delay_put()
99 dev_err(component->dev, "Can't change group delay while ADC are ON\n"); in cs4234_dac14_grp_delay_put()
100 goto exit; in cs4234_dac14_grp_delay_put()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/synaptics/ |
| D | as370.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-1.0";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 compatible = "arm,cortex-a53";
29 enable-method = "psci";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a72";
30 cpu-idle-states = <&CPU_PW20>;
31 next-level-cache = <&cluster0_l2>;
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| D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 cluster0_opp: opp-table-0 {
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| D | mt8183.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "mt8183-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
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| /kernel/linux/linux-5.10/Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
58 ---------------
70 performance penalty and a fixed latency. Mitigation can be increased
78 |------- -------
81 <------>
82 idle <---------------------->
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