| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
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| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
46 const: arm,psci-0.2
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
28 const: domain-idle-state
30 entry-latency-us:
32 The worst case latency in microseconds required to enter the idle
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| D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
24 \#power-domain-cells property in the PM domain provider node.
28 pattern: "^(power-controller|power-domain)([@-].*)?$"
30 domain-idle-states:
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| /kernel/linux/linux-5.10/Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
66 multiple individual single-core "processors", referred to as *hardware threads*
67 (or hyper-threads specifically on Intel hardware), that each can follow one
78 ---------
107 next wakeup event, or there are strict latency constraints preventing any of the
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| D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in :doc:`cpuidle`),
65 `below <intel-idle-parameters_>`_.]
82 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
85 initialized to represent a "polling idle state" (a pseudo-idle state in which
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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| /kernel/linux/linux-5.10/tools/power/cpupower/utils/ |
| D | cpuidle-set.c | 1 // SPDX-License-Identifier: GPL-2.0
19 {"disable-by-latency", required_argument, NULL, 'D'},
20 {"enable-all", no_argument, NULL, 'E'},
30 unsigned long long latency = 0, state_latency; in cmd_idle_set() local
36 if (ret == -1) in cmd_idle_set()
45 param = -1; in cmd_idle_set()
54 param = -1; in cmd_idle_set()
63 param = -1; in cmd_idle_set()
68 latency = strtoull(optarg, &endptr, 10); in cmd_idle_set()
70 printf(_("Bad latency value: %s\n"), optarg); in cmd_idle_set()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
31 state. Retention may have a slightly higher latency than Standby.
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
52 power modes possible at this state is vast, the exit latency and the residency
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
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| /kernel/linux/linux-5.10/drivers/cpuidle/governors/ |
| D | menu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * menu.c - the menu idle governor
5 * Copyright (C) 2006-2007 Adam Belay <abelay@novell.com>
36 * 3) Latency tolerance (from pmqos infrastructure)
40 * -----------------------
41 * C state entry and exit have an energy cost, and a certain amount of time in
68 * Repeatable-interval-detector
69 * ----------------------------
79 * ---------------------------
80 * C states, especially those with large exit latencies, can have a real
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | dt_idle_states.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "DT idle-states: " fmt
33 idle_state->enter = match_id->data; in init_state_node()
39 idle_state->enter_s2idle = match_id->data; in init_state_node()
41 err = of_property_read_u32(state_node, "wakeup-latency-us", in init_state_node()
42 &idle_state->exit_latency); in init_state_node()
46 err = of_property_read_u32(state_node, "entry-latency-us", in init_state_node()
49 pr_debug(" * %pOF missing entry-latency-us property\n", in init_state_node()
51 return -EINVAL; in init_state_node()
54 err = of_property_read_u32(state_node, "exit-latency-us", in init_state_node()
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| D | cpuidle-pseries.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * cpuidle-pseries - idle state cpuidle driver.
78 * were soft-disabled in check_and_cede_processor()
92 * "ibm,get-systems-parameter" RTAS call with the token
98 * table with all the parameters to ibm,get-system-parameters.
99 * CEDE_LATENCY_TOKEN corresponds to the token value for Cede Latency
105 * If the platform supports the cede latency settings information system
109 * a. The first byte is the length “N” of each cede latency setting record minus
112 * b. For each supported cede latency setting a cede latency setting record
115 * -----------------------------
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| /kernel/linux/linux-5.10/tools/testing/selftests/ftrace/test.d/trigger/ |
| D | trigger-trace-marker-synthetic-kernel.tc | 2 # SPDX-License-Identifier: GPL-2.0
3 # description: trace_marker trigger - test histogram with synthetic event against kernel event
12 echo "Test histogram kernel event to trace_marker latency histogram trigger"
14 echo 'latency u64 lat' > synthetic_events
16 echo 'hist:keys=common_pid:lat=common_timestamp.usecs-$ts0:onmatch(sched.sched_waking).latency($lat…
17 echo 'hist:keys=common_pid,lat:sort=lat' > events/synthetic/latency/trigger
24 grep 'hitcount: *1$' events/synthetic/latency/hist > /dev/null || \
27 exit 0
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| D | trigger-trace-marker-synthetic.tc | 2 # SPDX-License-Identifier: GPL-2.0
3 # description: trace_marker trigger - test histogram with synthetic event
12 echo "Test histogram trace_marker to trace_marker latency histogram trigger"
14 echo 'latency u64 lat' > synthetic_events
16 echo 'hist:keys=common_pid:lat=common_timestamp.usecs-$ts0:onmatch(ftrace.print).latency($lat) if b…
17 echo 'hist:keys=common_pid,lat:sort=lat' > events/synthetic/latency/trigger
18 echo -n "start" > trace_marker
19 echo -n "end" > trace_marker
21 cnt=`grep 'hitcount: *1$' events/ftrace/print/hist | wc -l`
23 if [ $cnt -ne 2 ]; then
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm630.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
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| /kernel/linux/linux-5.10/tools/testing/selftests/ftrace/test.d/preemptirq/ |
| D | irqsoff_tracer.tc | 2 # SPDX-License-Identifier: GPL-2.0
46 grep -q "tracer: preemptoff" trace || fail
49 egrep -q "5.....us : <stack trace>" trace || fail
51 # Check for 500ms of latency
52 egrep -q "latency: 5..... us" trace || fail
69 grep -q "tracer: irqsoff" trace || fail
72 egrep -q "5.....us : <stack trace>" trace || fail
74 # Check for 500ms of latency
75 egrep -q "latency: 5..... us" trace || fail
78 exit 0
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| /kernel/linux/linux-5.10/drivers/pci/pcie/ |
| D | aspm.c | 1 // SPDX-License-Identifier: GPL-2.0
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
69 /* Exit latencies */
70 struct aspm_latency latency_up; /* Upstream direction exit latency */
71 struct aspm_latency latency_dw; /* Downstream direction exit latency */
121 return link->aspm_default; in policy_to_aspm_state()
137 return link->clkpm_default; in policy_to_clkpm_state()
145 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
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| /kernel/linux/linux-5.10/drivers/iio/imu/inv_icm42600/ |
| D | inv_icm42600_buffer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
71 *accel = &pack2->accel; in inv_icm42600_fifo_decode_packet()
72 *gyro = &pack2->gyro; in inv_icm42600_fifo_decode_packet()
73 *temp = &pack2->temp; in inv_icm42600_fifo_decode_packet()
74 *timestamp = &pack2->timestamp; in inv_icm42600_fifo_decode_packet()
80 *accel = &pack1->data; in inv_icm42600_fifo_decode_packet()
82 *temp = &pack1->temp; in inv_icm42600_fifo_decode_packet()
90 *gyro = &pack1->data; in inv_icm42600_fifo_decode_packet()
91 *temp = &pack1->temp; in inv_icm42600_fifo_decode_packet()
97 return -EINVAL; in inv_icm42600_fifo_decode_packet()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /kernel/linux/linux-5.10/drivers/media/pci/mantis/ |
| D | mantis_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
35 err = i2c_transfer(&mantis->adapter, msg, 2); in read_eeprom_byte()
51 mantis->mac_address[0] = 0x08; in get_mac_address()
52 err = read_eeprom_byte(mantis, &mantis->mac_address[0], 6); in get_mac_address()
59 " MAC Address=[%pM]\n", mantis->mac_address); in get_mac_address()
74 switch (mantis->subsystem_device) { in mantis_load_config()
75 case MANTIS_VP_1033_DVB_S: /* VP-1033 */ in mantis_load_config()
76 mantis->hwconfig = &vp1033_mantis_config; in mantis_load_config()
78 case MANTIS_VP_1034_DVB_S: /* VP-1034 */ in mantis_load_config()
79 mantis->hwconfig = &vp1034_mantis_config; in mantis_load_config()
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | scpi-cpufreq.c | 41 struct scpi_data *priv = policy->driver_data; in scpi_cpufreq_get_rate()
42 unsigned long rate = clk_get_rate(priv->clk); in scpi_cpufreq_get_rate()
50 u64 rate = policy->freq_table[index].frequency * 1000; in scpi_cpufreq_set_target()
51 struct scpi_data *priv = policy->driver_data; in scpi_cpufreq_set_target()
54 ret = clk_set_rate(priv->clk, rate); in scpi_cpufreq_set_target()
59 if (clk_get_rate(priv->clk) != rate) in scpi_cpufreq_set_target()
60 return -EIO; in scpi_cpufreq_set_target()
71 domain = scpi_ops->device_domain_id(cpu_dev); in scpi_get_sharing_cpus()
76 if (cpu == cpu_dev->id) in scpi_get_sharing_cpus()
83 tdomain = scpi_ops->device_domain_id(tcpu_dev); in scpi_get_sharing_cpus()
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | resctrl_ui.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl
47 pseudo-locking is a unique way of using cache control to "pin" or
49 "Cache Pseudo-Locking".
86 own settings for cache use which can over-ride
118 Corresponding region is pseudo-locked. No
138 non-linear. This field is purely informational
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