| /kernel/linux/linux-5.10/Documentation/admin-guide/hw-vuln/ |
| D | l1tf.rst | 148 'L1D vulnerable' L1D flushing is disabled
176 Flushing the L1D evicts not only the data which should not be accessed
178 data. Flushing the L1D has a performance impact as the processor has to
191 The conditional mode avoids L1D flushing after VMEXITs which execute
373 the hypervisors, i.e. unconditional L1D flushing
386 mitigation, i.e. conditional L1D flushing
395 i.e. conditional L1D flushing.
413 The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`.
421 The KVM hypervisor mitigation mechanism, flushing the L1D cache when
466 To avoid the overhead of the default L1D flushing on VMENTER the
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
56 Here we are flushing a specific range of (user) virtual
104 Next, we have the cache flushing interfaces. In general, when Linux
126 The cache flushing routines below need only deal with cache flushing
161 Here we are flushing a specific range of (user) virtual
211 Here in these two interfaces we are flushing a specific range
337 Any necessary cache flushing or other coherency operations
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | mmu.h | 21 * Any code that needs to do any sort of TLB flushing for this
24 * flushing code keep track of what needs flushing.
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| D | tlbflush.h | 149 * isn't aware of PCID will end up harmlessly flushing
171 * TLB flushing:
180 * ..but the i386 has somewhat limited tlb flushing capabilities,
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| D | set_memory.h | 21 * - Flushing TLBs
22 * - Flushing CPU caches
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| /kernel/linux/linux-5.10/arch/parisc/include/asm/ |
| D | tlbflush.h | 5 /* TLB flushing routines.... */
33 * and not flushing the whole tlb.
41 /* Except for very small threads, flushing the whole TLB is in flush_tlb_mm()
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| /kernel/linux/linux-5.10/fs/btrfs/ |
| D | space-info.c | 59 * MAKING RESERVATIONS, FLUSHING NORMALLY (non-priority)
88 * MAKING RESERVATIONS, FLUSHING HIGH PRIORITY
95 * THE FLUSHING STATES
138 * above flushing first and then commit the transaction as the last resort.
323 * If we aren't flushing all things, let us overcommit up to in calc_available_free_space()
506 * make sure we're flushing enough delalloc to hopefully reclaim in shrink_delalloc()
768 * We may be flushing because suddenly we have less space than we had in btrfs_calc_reclaim_metadata_size()
771 * appropriate pressure on the flushing state machine. in btrfs_calc_reclaim_metadata_size()
847 * maybe_fail_all_tickets - we've exhausted our flushing, start failing tickets
849 * @space_info - the space info we were flushing
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | pti.rst | 96 allows us to skip flushing the entire TLB when switching page
119 h. INVPCID is a TLB-flushing instruction which allows flushing
123 flushing a kernel address, we need to flush all PCIDs, so a
124 single kernel address flush will require a TLB-flushing CR3
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/ |
| D | tlbflush.h | 6 * TLB flushing:
20 * TLB flushing for software loaded TLB chips
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| /kernel/linux/linux-5.10/arch/openrisc/include/asm/ |
| D | cacheflush.h | 20 * Helper function for flushing or invalidating entire pages from data
28 * Data cache flushing always happen on the local cpu. Instruction cache
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | mm.h | 15 * is reserved for VIPT aliasing flushing by generic code.
22 /* PFN alias flushing, for VIPT caches */
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| /kernel/linux/linux-5.10/drivers/md/bcache/ |
| D | journal.h | 25 * moving gc we work around it by flushing the btree to disk before updating the
74 * If the journal fills up, we start flushing dirty btree nodes until we can
75 * allocate space for a journal write again - preferentially flushing btree
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| /kernel/linux/linux-5.10/mm/ |
| D | percpu-vm.c | 121 * unmapped. Flush cache. As each flushing trial can be very
179 * returned to vmalloc as vmalloc will handle TLB flushing lazily.
181 * As with pcpu_pre_unmap_flush(), TLB flushing also is done at once
251 * As with pcpu_pre_unmap_flush(), TLB flushing also is done at once
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | tlbflush_32.c | 2 * TLB flushing operations for SH with an MMU.
130 * This is the most destructive of the TLB flushing options, in __flush_tlb_global()
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| /kernel/linux/linux-5.10/arch/sh/include/asm/ |
| D | cacheflush.h | 8 * Cache flushing:
12 * - flush_cache_dup mm(mm) handles cache flushing when forking
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| /kernel/linux/linux-5.10/drivers/ssb/ |
| D | driver_gige.c | 212 /* Write flushing is controlled by the Flush Status Control register. in ssb_gige_probe()
214 * to disable the IRQ mask while flushing to avoid concurrency. in ssb_gige_probe()
215 * Note that automatic write flushing does _not_ work from in ssb_gige_probe()
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| /kernel/linux/linux-5.10/drivers/accessibility/speakup/ |
| D | synth.c | 41 .flushing = 0,
78 if (speakup_info.flushing) { in _spk_do_catch_up()
79 speakup_info.flushing = 0; in _spk_do_catch_up()
199 speakup_info.flushing = 1; in spk_do_flush()
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| D | speakup_soft.c | 221 if (!synth_buffer_empty() || speakup_info.flushing) in softsynthx_read()
245 if (speakup_info.flushing) { in softsynthx_read()
246 speakup_info.flushing = 0; in softsynthx_read()
342 (!synth_buffer_empty() || speakup_info.flushing)) in softsynth_poll()
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| /kernel/linux/linux-5.10/Documentation/block/ |
| D | writeback_cache_control.rst | 45 worry if the underlying devices need any explicit cache flushing and how
71 driver needs to tell the block layer that it supports flushing caches by
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | cacheflush.h | 16 /* Cache flushing:
20 * - flush_cache_dup mm(mm) handles cache flushing when forking
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| /kernel/linux/linux-5.10/arch/powerpc/mm/book3s32/ |
| D | tlb.c | 3 * This file contains the routines for TLB flushing.
62 * TLB flushing:
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| /kernel/linux/linux-5.10/include/trace/events/ |
| D | jbd2.h | 261 __field( unsigned long, flushing )
275 __entry->flushing = stats->rs_flushing;
283 "locked %u flushing %u logging %u handle_count %u "
290 jiffies_to_msecs(__entry->flushing),
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| /kernel/linux/linux-5.10/fs/ceph/ |
| D | caps.c | 1355 int flushing, u64 flush_tid, u64 oldest_flush_tid) in __prep_cap() argument
1388 arg->follows = flushing ? ci->i_head_snapc->seq : 0; in __prep_cap()
1402 if (flushing & CEPH_CAP_XATTR_EXCL) { in __prep_cap()
1420 arg->dirty = flushing; in __prep_cap()
1459 pr_err("error allocating cap msg: ino (%llx.%llx) flushing %s tid %llu, requeuing cap.\n", in __send_cap()
1783 * Remove cap_flush from the mdsc's or inode's flushing cap list.
1817 * Add dirty inode to the flushing list. Assigned a seq number so we
1829 int flushing; in __mark_caps_flushing() local
1836 flushing = ci->i_dirty_caps; in __mark_caps_flushing()
1837 dout("__mark_caps_flushing flushing %s, flushing_caps %s -> %s\n", in __mark_caps_flushing()
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| /kernel/linux/linux-5.10/arch/arm/mach-ebsa110/include/mach/ |
| D | memory.h | 17 * Cache flushing area - SRAM
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | cache.h | 2 /* cache.h: Cache specific code for the Sparc. These include flushing
|