/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) 30 - const: gpll0 66 clock-names = "xo", "gpll0";
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D | qcom,gpucc.yaml | 33 - description: GPLL0 main branch source 34 - description: GPLL0 div branch source
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D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC 29 - description: GPLL0 div source from GCC
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D | qcom,sc7180-dispcc.yaml | 25 - description: GPLL0 source from GCC
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D | qcom,mmcc.yaml | 45 - const: gpll0
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/ |
D | qcom,osm-l3.yaml | 53 #define GPLL0 165 60 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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/kernel/linux/linux-5.10/drivers/clk/qcom/ |
D | gcc-sc7180.c | 36 static struct clk_alpha_pll gpll0 = { variable 43 .name = "gpll0", 69 .hw = &gpll0.clkr.hw, 82 .hw = &gpll0.clkr.hw, 170 { .hw = &gpll0.clkr.hw }, 177 { .hw = &gpll0.clkr.hw }, 192 { .hw = &gpll0.clkr.hw }, 209 { .hw = &gpll0.clkr.hw }, 224 { .hw = &gpll0.clkr.hw }, 238 { .hw = &gpll0.clkr.hw }, [all …]
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D | mmcc-msm8998.c | 56 .fw_name = "gpll0", 57 .name = "gpll0" 375 { .fw_name = "gpll0", .name = "gpll0" }, 391 { .fw_name = "gpll0", .name = "gpll0" }, 409 { .fw_name = "gpll0", .name = "gpll0" }, 427 { .fw_name = "gpll0", .name = "gpll0" }, 447 { .fw_name = "gpll0", .name = "gpll0" }, 467 { .fw_name = "gpll0", .name = "gpll0" }, 487 { .fw_name = "gpll0", .name = "gpll0" }, 509 { .fw_name = "gpll0", .name = "gpll0" },
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D | gcc-sdm660.c | 48 "gpll0", 59 "gpll0", 71 "gpll0", 107 "gpll0", 123 "gpll0", 137 "gpll0", 179 static struct clk_alpha_pll_postdiv gpll0 = { variable 183 .name = "gpll0", 1587 "gpll0", 1653 "gpll0", [all …]
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D | gcc-sdm845.c | 47 "gpll0", 62 "gpll0", 88 "gpll0", 112 "gpll0", 120 "gpll0", 127 "gpll0", 133 "gpll0", 147 "gpll0", 153 static struct clk_alpha_pll gpll0 = { variable 160 .name = "gpll0", [all …]
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D | gcc-ipq6018.c | 82 static struct clk_alpha_pll_postdiv gpll0 = { variable 87 .name = "gpll0", 98 { .hw = &gpll0.clkr.hw}, 294 { .hw = &gpll0.clkr.hw }, 373 { .hw = &gpll0.clkr.hw }, 426 { .hw = &gpll0.clkr.hw }, 477 { .hw = &gpll0.clkr.hw }, 632 { .hw = &gpll0.clkr.hw }, 666 { .hw = &gpll0.clkr.hw }, 911 { .hw = &gpll0.clkr.hw }, [all …]
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D | gpucc-msm8998.c | 94 { .fw_name = "gpll0", .name = "gpll0" },
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D | gcc-ipq8074.c | 53 "gpll0", 70 "gpll0", 84 "gpll0", 97 "gpll0", 111 "gpll0", 162 "gpll0", 176 "gpll0", 191 "gpll0", 205 "gpll0", 217 "gpll0", [all …]
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D | gcc-sm8250.c | 36 static struct clk_alpha_pll gpll0 = { variable 43 .name = "gpll0", 68 .hw = &gpll0.clkr.hw, 117 { .hw = &gpll0.clkr.hw }, 123 { .hw = &gpll0.clkr.hw }, 136 { .hw = &gpll0.clkr.hw }, 169 { .hw = &gpll0.clkr.hw }, 184 { .hw = &gpll0.clkr.hw }, 1395 .hw = &gpll0.clkr.hw, 1535 .hw = &gpll0.clkr.hw, [all …]
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D | gcc-sm8150.c | 37 static struct clk_alpha_pll gpll0 = { variable 44 .name = "gpll0", 73 .hw = &gpll0.clkr.hw, 125 { .hw = &gpll0.clkr.hw }, 140 { .hw = &gpll0.clkr.hw }, 166 { .hw = &gpll0.clkr.hw }, 190 { .hw = &gpll0.clkr.hw }, 206 { .hw = &gpll0.clkr.hw }, 222 { .hw = &gpll0.clkr.hw }, 1617 &gpll0.clkr.hw }, [all …]
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D | gcc-msm8996.c | 56 "gpll0" 77 "gpll0", 89 "gpll0", 101 "gpll0", 114 "gpll0", 128 "gpll0", 144 "gpll0", 163 "gpll0", 208 static struct clk_alpha_pll_postdiv gpll0 = { variable 212 .name = "gpll0", [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
D | cpufreq-qcom-hw.txt | 16 Definition: clock handle for XO clock and GPLL0 clock. 167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
D | qcom,gcc-msm8994.h | 11 #define GPLL0 1 macro
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D | qcom,gcc-sc7180.h | 11 #define GPLL0 1 macro
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D | qcom,gcc-sdm660.h | 111 #define GPLL0 101 macro
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D | qcom,gcc-msm8916.h | 9 #define GPLL0 0 macro
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D | qcom,gcc-msm8939.h | 9 #define GPLL0 0 macro
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D | qcom,gcc-sdm845.h | 175 #define GPLL0 165 macro
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D | qcom,gcc-sm8150.h | 207 #define GPLL0 197 macro
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D | qcom,gcc-ipq6018.h | 9 #define GPLL0 0 macro
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