Home
last modified time | relevance | path

Searched +full:inter +full:- +full:processor (Results 1 – 25 of 69) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This driver provides support for inter-processor communication
78 between CPU cores and MCU processor on Some Rockchip SOCs.
161 providing an interface for invoking the inter-process communication
162 signals from the application processor to other masters.
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
[all …]
/kernel/linux/linux-5.10/drivers/firmware/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 IVC (Inter-VM Communication) protocol is part of the IPC
9 (Inter Processor Communication) framework on Tegra. It maintains the
18 BPMP (Boot and Power Management Processor) is designed to off-loading
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dqcom-ipcc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
[all …]
Dxlnx,zynqmp-ipi-mailbox.txt4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
8 +-------------------------------------+
10 +-------------------------------------+
11 +--------------------------------------------------+
15 +--------------------------+ |
18 +--------------------------------------------------+
19 +------------------------------------------+
20 | +----------------+ +----------------+ |
24 | +----------------+ +----------------+ |
27 +------------------------------------------+
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-scb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "cx18-mailbox.h"
14 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
65 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 /* Offset where to find the Inter-Processor Communication data */
96 /* These fields form Inter-Processor Communication data which is used
102 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
/kernel/linux/linux-5.10/arch/arc/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
26 #include <asm/processor.h>
55 return -EINVAL; in arc_get_cpu_map()
58 return -EINVAL; in arc_get_cpu_map()
65 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
71 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
72 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/
Dqcom,fastrpc.txt3 The FastRPC implements an IPC (Inter-Processor Communication)
6 to offload tasks to the DSP and free up the application processor for
9 - compatible:
14 - label
20 - #address-cells
25 - #size-cells
33 - All Compute context banks MUST contain the following properties:
35 - compatible:
38 Definition: must be "qcom,fastrpc-compute-cb"
40 - reg
[all …]
/kernel/linux/linux-5.10/arch/ia64/include/asm/
Dhw_irq.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/mtk-vcodec/
Dvenc_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct venc_vpu_inst - encoder VPU driver instance
24 * @id: the id of inter-processor interrupt
Dvenc_ipi_msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * enum venc_ipi_msg_id - message id between AP and VPU
17 * (ipi stands for inter-processor interrupt)
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
91 * struct venc_ap_ipi_msg_enc_ext - AP to SCP extended enc cmd structure
104 * struct venc_ap_ipi_msg_deinit - AP to VPU deinit cmd structure
115 * enum venc_ipi_msg_status - VPU ack AP cmd status
123 * struct venc_vpu_ipi_msg_common - VPU ack AP cmd common structure
[all …]
/kernel/linux/linux-5.10/include/linux/remoteproc/
Dmtk_scp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * enum ipi_id - the id of inter-processor interrupt
/kernel/linux/linux-5.10/arch/mips/kernel/
Dsmp-up.c6 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
14 * Send inter-processor interrupt
58 return -ENOSYS; in up_cpu_disable()
/kernel/linux/linux-5.10/Documentation/virt/kvm/devices/
Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_ID.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
56 * Current processor priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
45 **Digital Signal Processor**
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
101 **Image Signal Processor**
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/mtk-vpu/
Dmtk_vpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
13 * VPU (video processor unit) is a tiny processor controlling video hardware
23 * enum ipi_id - the id of inter-processor interrupt
65 * enum rst_id - reset id to register reset function for VPU watchdog timeout
80 * vpu_ipi_register - register an ipi function
96 * vpu_ipi_send - send data from AP to vpu.
103 * This function is thread-safe. When this function returns,
115 * vpu_get_plat_device - get VPU's platform device
126 * vpu_wdt_reg_handler - register a VPU watchdog handler
[all …]
/kernel/linux/linux-5.10/sound/soc/intel/skylake/
Dcnl-sst-dsp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016-17, Intel Corporation.
21 /* Intel HD Audio Inter-Processor Communication Registers */
67 #define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1)
69 /* core reset - asserted high */
73 /* core run/stall - when set to 1 core is stalled */
77 /* set power active - when set to 1 turn core on */
81 /* current power active - power status of cores, set by hardware */
/kernel/linux/linux-5.10/arch/powerpc/platforms/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
35 bool "ePAPR para-virtualization support"
37 Enables ePAPR para-virtualization support for guests.
46 a hypervisor. This option is not user-selectable but should
62 bool "Device-tree based CPU feature discovery & setup"
121 registers are used for inter-processor communication.
203 bool "On-chip CPU temperature sensor support"
206 G3 and G4 processors have an on-chip temperature sensor called the
207 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
208 temperature within 2-4 degrees Celsius. This option shows the current
[all …]
/kernel/linux/linux-5.10/arch/x86/include/asm/
Dhyperv-tlfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
73 * than inter-processor interrupts
78 * EOI, ICR and TPR rather than their memory-mapped counterparts
81 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
91 * Recommend not using Auto End-Of-Interrupt feature
107 * Virtual processor will never share a physical core with another virtual
108 * processor, except for virtual processors that are reported as sibling SMT
118 /* Hyper-V specific model specific registers (MSRs) */
[all …]
/kernel/linux/linux-5.10/drivers/firmware/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
15 set of operating system-independent software interfaces that are
17 interfaces for: Discovery and self-description of the interfaces
19 a given device or domain into the various power-saving states that
50 Cores(AP) and the System Control Processor(SCP). The MHU peripheral
51 provides a mechanism for inter-processor communication between SCP
102 bool "Add firmware-provided memory map to sysfs" if EXPERT
105 Add the firmware-provided (unmodified) memory map to /sys/firmware/memmap.
109 See also Documentation/ABI/testing/sysfs-firmware-memmap.
[all …]
/kernel/liteos_a/arch/arm/gic/
Dgic_v2.c2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
148 /* register inter-processor interrupt */ in HalIrqInit()
/kernel/linux/linux-5.10/arch/parisc/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 ** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
7 ** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org>
13 ** -grant (1/12/2001)
43 #include <asm/processor.h>
80 /********** SMP inter processor interrupt and communication routines */
131 ops = p->pending_ipi; in ipi_interrupt()
132 p->pending_ipi = 0; in ipi_interrupt()
205 p->pending_ipi |= 1 << op; in ipi_send()
206 gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa); in ipi_send()
[all …]
/kernel/linux/linux-5.10/drivers/hid/intel-ish-hid/ipc/
Dpci-ish.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2016, Intel Corporation.
22 #include "ishtp-dev.h"
23 #include "hw-ish.h"
45 * ish_event_tracer() - Callback function to dump trace messages
67 * ish_init() - Init function
83 dev_err(dev->devc, "ISH: hw start failed.\n"); in ish_init()
87 /* Start the inter process communication to ISH processor */ in ish_init()
90 dev_err(dev->devc, "ISHTP: Protocol init failed.\n"); in ish_init()
106 return !pm_suspend_via_firmware() || pdev->device == CHV_DEVICE_ID; in ish_should_enter_d0i3()
[all …]
/kernel/linux/linux-5.10/drivers/xen/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
32 2) control domain: xl mem-max <target-domain> <maxmem>
35 3) control domain: xl mem-set <target-domain> <memory>
51 …SUBSYSTEM=="memory", ACTION=="add", RUN+="/bin/sh -c '[ -f /sys$devpath/state ] && echo online > /…
145 bool "Add support for dma-buf grant access device driver extension"
150 dma-buf implementation. With this extension grant references to
151 the pages of an imported dma-buf can be exported for other domain
153 converted into a local dma-buf for local export.
156 tristate "User-space grant reference allocator driver"
162 or as part of an inter-domain shared memory channel.
[all …]

123