| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
|
| D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
[all …]
|
| D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
|
| D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| D | fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/fpga.c
5 * Interrupt handler for OMAP-1510 Innovator FPGA
35 unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; in fpga_mask_irq()
42 & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); in fpga_mask_irq()
45 & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2); in fpga_mask_irq()
68 unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; in fpga_unmask_irq()
75 | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); in fpga_unmask_irq()
78 | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); in fpga_unmask_irq()
107 .name = "FPGA-ack",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
|
| D | sodaville.txt | 14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
|
| D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
[all …]
|
| D | gpio-zynq.txt | 2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
[all …]
|
| D | gpio-omap.txt | 4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
[all …]
|
| D | gpio-xlp.txt | 10 -------------------
12 - compatible: Should be one of the following:
13 - "netlogic,xlp832-gpio": For Netlogic XLP832
14 - "netlogic,xlp316-gpio": For Netlogic XLP316
15 - "netlogic,xlp208-gpio": For Netlogic XLP208
16 - "netlogic,xlp980-gpio": For Netlogic XLP980
17 - "netlogic,xlp532-gpio": For Netlogic XLP532
18 - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
19 - reg: Physical base address and length of the controller's registers.
20 - #gpio-cells: Should be two. The first cell is the pin number and the second
[all …]
|
| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
[all …]
|
| D | gpio-mvebu.txt | 5 - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6 "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
8 "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9 Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
12 "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
15 "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
17 Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
20 - reg: Address and length of the register set for the device. Only one
21 entry is expected, except for the "marvell,armadaxp-gpio" variant
23 one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
[all …]
|
| D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | qcom-pdc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
58 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_get_irqchip_state()
68 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_set_irqchip_state()
76 int pin_out = d->hwirq; in pdc_enable_intr()
93 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_disable()
102 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_enable()
111 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_mask()
119 if (d->hwirq == GPIO_NO_WAKE_IRQ) in qcom_pdc_gic_unmask()
131 * Level sensitive active low LOW
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | qcom-pm8xxx.txt | 1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
16 - #address-cells:
21 - #size-cells:
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
39 number. The 2nd cell is the trigger type and level flags
42 1 = low-to-high edge triggered
43 2 = high-to-low edge triggered
[all …]
|
| /kernel/linux/linux-5.10/Documentation/virt/kvm/devices/ |
| D | xics.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_ID.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
|
| /kernel/linux/linux-5.10/Documentation/ia64/ |
| D | fsys.rst | 2 Light-weight System Calls for IA-64
5 Started: 13-Jan-2003
7 Last update: 27-Sep-2003
9 David Mosberger-Tang
14 "fsys-mode". To recap, the normal states of execution are:
16 - kernel mode:
18 switched over to kernel memory. The user-level state is saved
19 in a pt-regs structure at the top of the kernel memory stack.
21 - user mode:
23 user memory. The user-level state is contained in the
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/kvm/vgic/ |
| D | vgic-v2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/irqchip/arm-gic.h>
31 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; in vgic_v2_set_underflow()
33 cpuif->vgic_hcr |= GICH_HCR_UIE; in vgic_v2_set_underflow()
44 * - active bit is transferred as is
45 * - pending bit is
46 * - transferred as is in case of edge sensitive IRQs
47 * - set to the line-level (resample time) for level sensitive IRQs
51 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v2_fold_lr_state()
52 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; in vgic_v2_fold_lr_state()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/freescale/enetc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 level.
14 If compiled as module (M), the module name is fsl-enetc.
26 If compiled as module (M), the module name is fsl-enetc-vf.
35 If compiled as module (M), the module name is fsl-enetc-mdio.
47 If compiled as module (M), the module name is fsl-enetc-ptp.
50 bool "ENETC hardware Time-sensitive Network support"
53 There are Time-Sensitive Network(TSN) capabilities(802.1Qbv/802.1Qci
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-image-source.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _image-source-controls:
9 The Image Source control class is intended for low-level control of
15 .. _image-source-control-id:
28 same sub-device.
58 The unit cell consists of the whole area of the pixel, sensitive and
59 non-sensitive.
|
| /kernel/linux/linux-5.10/Documentation/virt/ |
| D | paravirt_ops.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low level critical instructions and high level
17 functionalities in various areas. pv-ops allows for optimizations at run
18 time by enabling binary patching of the low-ops critical operations
23 - simple indirect call
24 These operations correspond to high level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low level critical instructions. They
32 - a set of macros for hand written assembly code
[all …]
|