| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
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| D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
28 #address-cells = <1>;
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| D | spi-cadence.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
22 compatible = "xlnx,zynq-spi-r1p6";
23 clock-names = "ref_clk", "pclk";
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| D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
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| D | spi-bcm63xx.txt | 4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
27 clock-names = "spi";
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| D | spi-bcm63xx-hsspi.txt | 4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6328-hsspi";
27 clock-names = "hsspi", "pll";
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| D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO devicetree bindings
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: "/schemas/spi/spi-controller.yaml#"
21 const: spi-gpio
23 sck-gpios:
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| D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| D | spi-armada-3700.txt | 5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
18 compatible = "marvell,armada-3700-spi";
19 #address-cells = <1>;
20 #size-cells = <0>;
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| D | spi-zynq-qspi.txt | 2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
18 compatible = "xlnx,zynq-qspi-1.0";
20 interrupt-parent = <&intc>;
22 clock-names = "ref_clk", "pclk";
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| D | fsl-spi.txt | 4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
24 the cs-gpios property is not present.
28 cell-index = <0>;
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| D | spi-zynqmp-qspi.txt | 2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynqmp-qspi-1.0".
6 - reg : Physical base address and size of GQSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
18 compatible = "xlnx,zynqmp-qspi-1.0";
19 clock-names = "ref_clk", "pclk";
22 interrupt-parent = <&gic>;
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| /kernel/linux/linux-5.10/drivers/net/ethernet/pasemi/ |
| D | pasemi_mac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
78 struct pasemi_mac_csring *cs[MAX_CS]; member
94 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) argument
95 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) argument
96 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) argument
97 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) argument
98 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) argument
99 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) argument
101 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
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| /kernel/linux/linux-5.10/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | gpmc-nor.txt | 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
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| D | gpmc-onenand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
12 - compatible: "ti,omap2-onenand"
13 - reg: The CS line the peripheral is connected to
14 - gpmc,device-width: Width of the ONENAND device connected to the GPMC
19 - int-gpios: GPIO specifier for the INT pin.
23 - #address-cells: should be set to 1
24 - #size-cells: should be set to 1
29 compatible = "ti,omap3430-gpmc";
33 gpmc,num-cs = <8>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-synquacer.c | 1 // SPDX-License-Identifier: GPL-2.0
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
76 /* calculate the value of CS bits in CCR register on standard mode */
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
81 /* calculate the value of CS bits in CSR register on standard mode */
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
89 /* calculate the value of CS bits in CSR register on fast mode */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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| /kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_device.c | 7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
80 /* Num of desc for rx rings */
83 /* Num of desc for tx rings */
109 /* Num of desc for rx rings */
112 /* Num of desc for tx rings */
188 /* Num of desc for rx rings */
191 /* Num of desc for tx rings */
217 /* Num of desc for rx rings */
220 /* Num of desc for tx rings */
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | hi3519.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/hi3519-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
24 gic: interrupt-controller@10300000 {
25 compatible = "arm,cortex-a7-gic";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | ingenic-sysost.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ingenic,sysost.h>
79 struct clocksource cs; member
96 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_percpu_timer_recalc_rate()
99 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_percpu_timer_recalc_rate()
110 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_global_timer_recalc_rate()
113 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_global_timer_recalc_rate()
149 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_percpu_timer_set_rate()
153 val = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_percpu_timer_set_rate()
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