| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun6i-a31-pll6-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
23 const: allwinner,sun6i-a31-pll6-clk
47 compatible = "allwinner,sun6i-a31-pll6-clk";
50 clock-output-names = "pll6", "pll6x2";
|
| D | allwinner,sun4i-a10-pll6-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
23 const: allwinner,sun4i-a10-pll6-clk
47 compatible = "allwinner,sun4i-a10-pll6-clk";
50 clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
|
| D | allwinner,sun4i-a10-usb-clk.yaml | 116 clocks = <&pll6 1>;
126 clocks = <&pll6 1>;
|
| D | allwinner,sun5i-a13-ahb-clk.yaml | 48 clocks = <&axi>, <&cpu>, <&pll6 1>;
|
| D | allwinner,sun4i-a10-apb1-clk.yaml | 48 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-ahb-clk.yaml | 95 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
|
| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 259 * can work at speeds up to 300M, just after reparenting to pll6 in sun5i_a13_get_ahb_factors()
284 * if parent is pll6, then
285 * parent_rate = pll6 rate / (m + 1)
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
919 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1121 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1128 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
|
| D | clk-factors.c | 195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | allwinner,sun4i-a10-ahci.yaml | 45 clocks = <&pll6 0>, <&ahb_gates 25>;
|
| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-milbeaut.c | 23 #define M10V_PLL6 "pll6"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
|
| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 259 #define PLL6 250 macro
|
| D | qcom,gcc-msm8960.h | 291 #define PLL6 283 macro
|
| D | qcom,gcc-mdm9615.h | 293 #define PLL6 283 macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
|
| D | intel_dpll_mgr.c | 1885 temp |= pll->state.hw_state.pll6; in bxt_ddi_pll_enable()
2005 hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2006 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2169 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef); in bxt_ddi_set_dpll_hw_state()
2170 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl); in bxt_ddi_set_dpll_hw_state()
2269 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", in bxt_dump_hw_state()
2276 hw_state->pll6, in bxt_dump_hw_state()
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx6sll.c | 28 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
128 …hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, … in imx6sll_clocks_init()
|
| D | clk-vf610.c | 82 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
224 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); in vf610_clocks_init()
|
| D | clk-imx6sl.c | 68 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
221 hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6sl_clocks_init()
|
| D | clk-imx6ul.c | 26 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
154 hws[IMX6UL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6ul_clocks_init()
|
| D | clk-imx6q.c | 89 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
240 /* PLL6 bypass is not part of the assigned clock list */ in pll6_bypassed()
482 hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6q_clocks_init()
|
| D | clk-imx6sx.c | 82 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
165 hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6sx_clocks_init()
|
| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu-sun6i-a31.c | 1250 /* Force AHB1 to PLL6 / 3 */ in sun6i_a31_ccu_setup()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_setup()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_setup()
|