| /kernel/linux/linux-5.10/drivers/scsi/isci/ |
| D | port_config.c | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
72 * General port configuration agent routines
93 return -1; in sci_sas_address_compare()
97 return -1; in sci_sas_address_compare()
106 * @controller: The controller object used for the port search.
109 * This routine will find a matching port for the phy. This means that the
110 * port and phy both have the same broadcast sas address and same received sas
111 * address. The port address or the NULL if there is no matching
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| D | probe_roms.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
102 * by phys in the supplied port.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
109 } phys[SCI_MAX_PHYS]; member
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
199 * for any PORT. i.e. There are no phys assigned to any of the ports at start.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | hisilicon-hns-nic.txt | 4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
14 The remaining 6 PHYs are taken according to the mode of DSAF.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
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| D | ti,cpsw-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
24 - const: ti,cpsw-switch
25 - items:
26 - const: ti,am335x-cpsw-switch
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | libahci_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
36 * ahci_platform_enable_phys - Enable PHYs
39 * This function enables all the PHYs found in hpriv->phys, if any.
40 * If a PHY fails to be enabled, it disables all the PHYs already
50 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
51 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
55 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
57 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
61 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/xscale/ |
| D | ixp4xx_eth.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Ethernet port config (0x00 is not present on IXP42X):
9 * logical port 0x00 0x10 0x20
10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
13 * RX-free queue 26 27 28
14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
17 * bits 0 -> 1 - NPE ID (RX and TX-done)
18 * bits 0 -> 2 - priority (TX, per 802.1D)
19 * bits 3 -> 4 - port ID (user-set?)
20 * bits 5 -> 31 - physical descriptor address
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
32 root port to downstream device and host bridge drivers can do programming
33 which depends on CLKREQ signal existence. For example, programming root port
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
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| /kernel/linux/linux-5.10/drivers/phy/st/ |
| D | phy-stm32-usbphyc.c | 1 // SPDX-License-Identifier: GPL-2.0
71 struct stm32_usbphyc_phy **phys; member
99 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16 in stm32_usbphyc_get_pll_params()
105 pll_params->ndiv = (u8)ndiv; in stm32_usbphyc_get_pll_params()
109 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
110 pll_params->frac = (u16)frac; in stm32_usbphyc_get_pll_params()
116 u32 clk_rate = clk_get_rate(usbphyc->clk); in stm32_usbphyc_pll_init()
122 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n", in stm32_usbphyc_pll_init()
124 return -EINVAL; in stm32_usbphyc_pll_init()
136 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); in stm32_usbphyc_pll_init()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | ahci-platform.txt | 3 SATA nodes are defined to describe on-chip Serial ATA controllers.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
8 PHYs.
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
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| /kernel/linux/linux-5.10/sound/soc/qcom/qdsp6/ |
| D | q6asm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
21 #include "q6dsp-errno.h"
22 #include "q6dsp-common.h"
241 phys_addr_t phys; member
270 /* idx:1 out port, 0: in port */
271 struct audio_port_data port[2]; member
283 hdr->hdr_field = APR_SEQ_CMD_HDR_FIELD; in q6asm_add_hdr()
284 hdr->src_port = ((ac->session << 8) & 0xFF00) | (stream_id); in q6asm_add_hdr()
285 hdr->dest_port = ((ac->session << 8) & 0xFF00) | (stream_id); in q6asm_add_hdr()
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_rmu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
16 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
24 #include <linux/dma-mapping.h>
33 (((struct rio_priv *)(mport->priv))->rmm_handle)
35 /* RapidIO definition irq, which read from OF-tree */
36 #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
37 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
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| /kernel/linux/linux-5.10/arch/arm/mach-davinci/include/mach/ |
| D | uncompress.h | 2 * Serial port stubs for kernel decompress status messages
5 * arch/arm/plat-omap/include/mach/uncompress.h
24 #include <asm/mach-types.h>
32 /* PORT_16C550A, in polled non-fifo mode */
52 static inline void set_uart_info(u32 phys) in set_uart_info() argument
54 uart = (u32 *)phys; in set_uart_info()
57 #define _DEBUG_LL_ENTRY(machine, phys) \ argument
60 set_uart_info(phys); \
65 #define DEBUG_LL_DAVINCI(machine, port) \ argument
66 _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-sata.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
50 phys = <&sata0_phy0>;
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| /kernel/linux/linux-5.10/drivers/net/wan/ |
| D | ixp4xx_hss.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
13 #include <linux/dma-mapping.h>
83 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
136 /* 56k data endiannes - which bit unused: high (default) or low */
176 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
188 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
197 #define TDMMAP_HDLC 1 /* HDLC - packetized */
198 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
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| /kernel/linux/linux-5.10/Documentation/scsi/ |
| D | libsas.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 * SAS Phy/Port/HA event management (LLDD generates,
15 * SAS Port management (creation/destruction),
39 It will then return. Then you enable your phys to actually
47 ------------------
58 And then all the phys are an array of my_phy in your HA
61 Then as you go along and initialize your phys you also
65 In general, the phys are managed by the LLDD and the ports
66 are managed by the SAS layer. So the phys are initialized
75 - must be set (0/1)
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| /kernel/linux/linux-5.10/drivers/input/joystick/ |
| D | tmdc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 1998-2001 Vojtech Pavlik
6 * Trystan Larey-Williams
56 { ABS_X, ABS_Y, ABS_RUDDER, -1, ABS_THROTTLE };
74 } tmdc_hat_to_axis[] = {{ 0, 0}, { 1, 0}, { 0,-1}, {-1, 0}, { 0, 1}};
91 …{ 0, "Unknown %d-axis, %d-button TM device %d", 0, 0, { 0, 0 }, { 0, 0 }, tmdc_abs, tmdc_btn_joy…
98 char phys[32]; member
109 struct tmdc_port *port[2]; member
113 char phys[2][32];
164 data[k][i[k]] |= (~v & 1) << (j[k]++ - 1); /* Data bit */ in tmdc_read_packet()
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| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | io.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <asm-generic/iomap.h>
22 * Virtual -> physical identity mapping starts at this offset
34 * register not being up-to-date with respect to the hardware
46 /* Re-read to make sure it was written. */ in __set_hae()
65 return (unsigned long)address - IDENT_ADDR; in virt_to_phys()
75 unsigned long phys = (unsigned long)address; in virt_to_phys() local
77 /* Sign-extend from bit 41. */ in virt_to_phys()
78 phys <<= (64 - 41); in virt_to_phys()
79 phys = (long)phys >> (64 - 41); in virt_to_phys()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
27 - description:
30 reg-names:
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| D | cdns,dsi.txt | 7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
15 - #size-cells: must be set to 0.
18 - resets: DSI reset lines.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/ |
| D | hip04_eth.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
155 #define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
156 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
165 #define DRV_NAME "hip04-ether"
216 unsigned int port; member
253 return (head - tail) % TX_DESC_NUM; in tx_count()
261 priv->speed = speed; in hip04_config_port()
262 priv->duplex = duplex; in hip04_config_port()
264 switch (priv->phy_mode) { in hip04_config_port()
284 writel_relaxed(val, priv->base + GE_PORT_MODE); in hip04_config_port()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | allwinner,sun6i-a31-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-mipi-dsi
17 - allwinner,sun50i-a64-mipi-dsi
29 - description: Bus Clock
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| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 the following device-specific properties.
19 - Chen-Yu Tsai <wens@csie.org>
20 - Maxime Ripard <mripard@kernel.org>
23 "#phy-cells":
28 - const: allwinner,sun8i-a83t-dw-hdmi
29 - const: allwinner,sun50i-h6-dw-hdmi
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi"
13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-vbus";
37 regulator-min-microvolt = <5000000>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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