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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
24 - qcom,geni-se-qup
30 clock-names:
32 - const: m-ahb
33 - const: s-ahb
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
34 unsigned char arm, ahb, sel; member
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
[all …]
Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
46 static const char *per_sel_clks[] = { "ahb", "upll", };
47 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
140 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
142 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
143 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
144 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
[all …]
Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
74 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
75 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
76 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
93 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
111 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
122 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
123 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
141 for_each_compatible_node(osc_np, NULL, "fixed-clock") { in mx31_clocks_init_dt()
[all …]
Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
64 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
124 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
136 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
166 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
[all …]
Dclk-imx6sx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
37 static const char *pcie_axi_sels[] = { "axi", "ahb", };
61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
130 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
146 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
[all …]
/kernel/linux/linux-5.10/drivers/soc/versatile/
Dsoc-integrator.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,core-module-integrator", },
29 return "ASB little-endian"; in integrator_arch_str()
31 return "AHB little-endian"; in integrator_arch_str()
33 return "AHB-Lite system bus, bi-endian"; in integrator_arch_str()
35 return "AHB"; in integrator_arch_str()
37 return "AHB system bus, ASB processor bus"; in integrator_arch_str()
70 return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid)); in arch_show()
78 return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid)); in fpga_show()
113 return -ENODEV; in integrator_soc_init()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/qcom/camss/
Dcamss.c1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - Core
8 * Copyright (C) 2015-2018 Linaro Ltd.
11 #include <linux/media-bus-format.h>
22 #include <media/media-device.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mc.h>
26 #include <media/v4l2-fwnode.h>
37 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
117 .hw.init = CLK_HW_INIT("pll-ve",
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci_priv *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
142 /* clear the error(s) */ in rcar_pci_err_irq()
[all …]
/kernel/linux/linux-5.10/drivers/staging/octeon-usb/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
31 * This Software, including technical data, may be subject to U.S. export
32 * control laws, including the U.S. Export Administration Act and its associated
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
/kernel/linux/linux-5.10/arch/mips/ath25/
Dar2315_regs.h11 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
81 #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82 #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
92 /* AHB master arbitration control */
97 #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
106 #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
108 #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
128 /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
163 #define AR2315_ISR_AHB 0x00000008 /* AHB error */
172 #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
[all …]
Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
97 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
103 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
108 .name = "ar5312-misc",
153 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
155 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
169 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
174 .name = "physmap-flash",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath10k/
Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
14 #include "ahb.h"
17 { .compatible = "qcom,ipq4019-wifi",
30 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
61 #address-cells = <1>;
[all …]
Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/
Dcommon-pci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-ixp4xx/common-pci.c
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
26 #include <asm/dma-mapping.h>
87 pr_debug("%s failed\n", __func__); in check_master_abort()
105 * PCI workaround - only works if NP PCI space reads have in ixp4xx_pci_read_errata()
170 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | in ixp4xx_config_addr()
241 u8 bus_num = bus->number; in ixp4xx_pci_read_config()
264 u8 bus_num = bus->number; in ixp4xx_pci_write_config()
309 regs->ARM_pc += 4; in abort_handler()
[all …]
/kernel/linux/linux-5.10/drivers/clk/sprd/
Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx35-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
18 ---------------------------
27 ahb 8
105 const: fsl,imx35-ccm
113 '#clock-cells':
117 - compatible
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/
Daspeed-p2a-ctrl.txt2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
6 In this case, the host has access to a 64KiB window into all of the BMC's
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
23 to AHB mapping
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dqcom,msm-uartdm.txt3 The MSM serial UARTDM hardware is designed for high-speed use cases where the
4 transmit and/or receive channels can be offloaded to a dma-engine. From a
5 software perspective it's mostly compatible with the MSM serial UART except
9 - compatible: Should contain at least "qcom,msm-uartdm".
12 "qcom,msm-uartdm-v1.1"
13 "qcom,msm-uartdm-v1.2"
14 "qcom,msm-uartdm-v1.3"
15 "qcom,msm-uartdm-v1.4"
16 - reg: Should contain UART register locations and lengths. The first
19 "qcom,msm-uartdm-v1.3" is the only compatible value that might
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]

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