| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
24 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
26 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 Unlike most other PWM controllers, the SiFive PWM controller currently
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
29 - const: sifive,pwm0
[all …]
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| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
140 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
144 compatible = "sifive,plic-1.0.0";
[all …]
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| D | hifive-unleashed-a00.dts | 2 /* Copyright (c) 2018-2019 SiFive, Inc */
15 model = "SiFive HiFive Unleashed A00";
16 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
26 - const: sifive,fu540-c000-clint
27 - const: sifive,clint0
30 Should be "sifive,<chip>-clint" and "sifive,clint<version>".
32 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
33 onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
35 Please refer to sifive-blocks-ip-versioning.txt for details
53 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-uart
21 - const: sifive,uart0
24 Should be something similar to "sifive,<chip>-uart"
26 and "sifive,uart<version>" for the general UART IP
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
38 - Sagar Kadam <sagar.kadam@sifive.com>
39 - Paul Walmsley <paul.walmsley@sifive.com>
45 - const: sifive,fu540-c000-plic
46 - const: sifive,plic-1.0.0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
24 - const: sifive,fu540
|
| D | sifive-l2-cache.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
29 - sifive,fu540-c000-ccache
37 - const: sifive,fu540-c000-ccache
85 compatible = "sifive,fu540-c000-ccache", "cache";
|
| D | cpus.yaml | 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
30 - sifive,rocket0
31 - sifive,e5
32 - sifive,e51
33 - sifive,u54-mc
34 - sifive,u54
35 - sifive,u5
98 // Example 1: SiFive Freedom U540G Development Kit
105 compatible = "sifive,rocket0", "riscv";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | sifive,fu540-c000-pdma.yaml | 4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 - const: sifive,fu540-c000-pdma
51 compatible = "sifive,fu540-c000-pdma";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Yash Shah <yash.shah@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 - const: sifive,fu540-c000-gpio
17 - const: sifive,gpio0
55 #include <dt-bindings/clock/sifive-fu540-prci.h>
57 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/sifive/ |
| D | fu540-prci.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27 const: sifive,fu540-c000-prci
56 compatible = "sifive,fu540-c000-prci";
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| D | sifive_edac.c | 3 * SiFive Platform EDAC Driver
5 * Copyright (C) 2018-2019 SiFive, Inc.
13 #include <soc/sifive/sifive_l2_cache.h>
61 p->dci->mod_name = "Sifive ECC Manager"; in ecc_register()
117 MODULE_AUTHOR("SiFive Inc.");
118 MODULE_DESCRIPTION("SiFive platform EDAC driver");
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| /kernel/linux/linux-5.10/drivers/clk/sifive/ |
| D | Kconfig | 4 bool "SiFive SoC driver support"
7 SoC drivers for SiFive Linux-capable SoCs.
12 bool "PRCI driver for SiFive FU540 SoCs"
16 FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
|
| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | sifive.c | 3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
22 * - drivers/pwm/pwm-sifive.c
26 * SiFive FE310-G000 v2p3
28 * https://github.com/sifive/sifive-blocks/
30 * The SiFive UART design is not 8250-compatible. The following common
127 #define SIFIVE_SERIAL_NAME "sifive-serial"
129 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
155 * Configuration data specific to this SiFive UART.
189 * __ssp_early_writel() - write to a SiFive serial port register (early)
[all …]
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-sifive.c | 3 // Copyright 2018 SiFive, Inc.
5 // SiFive SPI controller driver (master mode only)
7 // Author: SiFive, Inc.
8 // sifive@sifive.com
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth", in sifive_spi_probe()
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word", in sifive_spi_probe()
431 { .compatible = "sifive,spi0", },
446 MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
447 MODULE_DESCRIPTION("SiFive SPI driver");
|
| /kernel/linux/linux-5.10/drivers/dma/sf-pdma/ |
| D | sf-pdma.h | 3 * SiFive FU540 Platform DMA driver
4 * Copyright (C) 2019 SiFive
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
|
| D | Kconfig | 2 tristate "Sifive PDMA controller driver"
7 Support the SiFive PDMA controller.
|
| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-sifive.c | 3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
310 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm); in pwm_sifive_probe()
347 { .compatible = "sifive,pwm0" },
356 .name = "pwm-sifive",
362 MODULE_DESCRIPTION("SiFive PWM driver");
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-sifive-plic.c | 3 * Copyright (C) 2017 SiFive
24 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
176 .name = "SiFive PLIC",
385 "irqchip/sifive/plic:starting", in plic_init()
401 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
|
| /kernel/linux/linux-5.10/drivers/soc/sifive/ |
| D | Kconfig | 6 bool "Sifive L2 Cache controller"
8 Support for the L2 cache controller on SiFive platforms.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | macb.txt | 18 Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
21 For "sifive,fu540-c000-gem", second range is required to specify the
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
|