| /kernel/linux/linux-5.10/drivers/gpu/drm/meson/ |
| D | meson_crtc.c | 158 priv->viu.osd1_enabled = false; in meson_g12a_crtc_atomic_disable()
159 priv->viu.osd1_commit = false; in meson_g12a_crtc_atomic_disable()
161 priv->viu.vd1_enabled = false; in meson_g12a_crtc_atomic_disable()
162 priv->viu.vd1_commit = false; in meson_g12a_crtc_atomic_disable()
183 priv->viu.osd1_enabled = false; in meson_crtc_atomic_disable()
184 priv->viu.osd1_commit = false; in meson_crtc_atomic_disable()
186 priv->viu.vd1_enabled = false; in meson_crtc_atomic_disable()
187 priv->viu.vd1_commit = false; in meson_crtc_atomic_disable()
225 priv->viu.osd1_commit = true; in meson_crtc_atomic_flush()
226 priv->viu.vd1_commit = true; in meson_crtc_atomic_flush()
[all …]
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| D | meson_overlay.c | 361 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1; in meson_overlay_setup_scaler_params()
382 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; in meson_overlay_setup_scaler_params()
384 priv->viu.vpp_vsc_ini_phase = vphase << 8; in meson_overlay_setup_scaler_params()
385 priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) | in meson_overlay_setup_scaler_params()
388 priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) | in meson_overlay_setup_scaler_params()
390 priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) | in meson_overlay_setup_scaler_params()
393 priv->viu.viu_vd1_fmt_w = in meson_overlay_setup_scaler_params()
397 priv->viu.vd1_afbc_vd_cfmt_w = in meson_overlay_setup_scaler_params()
401 priv->viu.vd1_afbc_vd_cfmt_h = in meson_overlay_setup_scaler_params()
404 priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) | in meson_overlay_setup_scaler_params()
[all …]
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| D | meson_plane.c | 114 line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7; in meson_g12a_afbcd_line_stride()
121 line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7; in meson_g12a_afbcd_line_stride()
160 priv->viu.osd1_afbcd = true; in meson_plane_atomic_update()
162 priv->viu.osd1_afbcd = false; in meson_plane_atomic_update()
165 priv->viu.osd1_ctrl_stat = OSD_ENABLE | in meson_plane_atomic_update()
169 priv->viu.osd1_ctrl_stat2 = readl(priv->io_base + in meson_plane_atomic_update()
175 priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL; in meson_plane_atomic_update()
177 if (priv->viu.osd1_afbcd) { in meson_plane_atomic_update()
180 priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR; in meson_plane_atomic_update()
181 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE; in meson_plane_atomic_update()
[all …]
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| D | meson_osd_afbcd.c | 136 priv->viu.osd1_width) | in meson_gxm_afbcd_setup()
138 priv->viu.osd1_height), in meson_gxm_afbcd_setup()
141 writel_relaxed(priv->viu.osd1_addr >> 4, in meson_gxm_afbcd_setup()
143 writel_relaxed(priv->viu.osd1_addr >> 4, in meson_gxm_afbcd_setup()
146 writel_relaxed((0xe4 << 24) | (priv->viu.osd1_addr & 0xffffff), in meson_gxm_afbcd_setup()
149 if (priv->viu.osd1_width <= 128) in meson_gxm_afbcd_setup()
151 else if (priv->viu.osd1_width <= 256) in meson_gxm_afbcd_setup()
153 else if (priv->viu.osd1_width <= 512) in meson_gxm_afbcd_setup()
155 else if (priv->viu.osd1_width <= 1024) in meson_gxm_afbcd_setup()
157 else if (priv->viu.osd1_width <= 2048) in meson_gxm_afbcd_setup()
[all …]
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| D | meson_vpp.h | 15 /* Mux VIU/VPP to ENCI */
17 /* Mux VIU/VPP to ENCP */
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| D | meson_viu.c | 21 * VIU Handles the Pixel scanout and the basic Colorspace conversions
314 /* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
503 priv->viu.osd1_enabled = false; in meson_viu_init()
504 priv->viu.osd1_commit = false; in meson_viu_init()
505 priv->viu.osd1_interlace = false; in meson_viu_init()
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| D | meson_osd_afbcd.h | 12 /* This is an internal address used to transfer pixel from AFBC to the VIU */
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| D | meson_drv.h | 150 } viu; member
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| D | meson_vpp.c | 18 * VPP Handles all the Post Processing after the Scanout from the VIU
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| D | meson_venc.c | 38 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
1146 /* Select ENCI for VIU */ in meson_venc_hdmi_mode_set()
1514 /* Select ENCP for VIU */ in meson_venc_hdmi_mode_set()
1643 /* Internal Venc, Internal VIU Sync, Internal Vencoder */ in meson_venci_cvbs_mode_set()
1702 /* Select ENCI for VIU */ in meson_venci_cvbs_mode_set()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-ee-pwrc.yaml | 79 - const: viu
95 - const: viu
120 - const: viu
139 - const: viu
180 reset-names = "viu", "venc", "vcbus", "bt656",
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| /kernel/linux/linux-5.10/drivers/media/platform/ |
| D | fsl-viu.c | 5 * Freescale VIU video driver
52 printk(KERN_DEBUG "viu: " fmt , ## arg); \
178 * Macro definitions of VIU registers
354 dprintk(1, "viu/0: [%p/%d] timeout\n", buf, buf->vb.i); in viu_vid_timeout()
563 strscpy(cap->driver, "viu", sizeof(cap->driver)); in vidioc_querycap()
564 strscpy(cap->card, "viu", sizeof(cap->card)); in vidioc_querycap()
565 strscpy(cap->bus_info, "platform:viu", sizeof(cap->bus_info)); in vidioc_querycap()
895 #define decoder_call(viu, o, f, args...) \ argument
896 v4l2_subdev_call(viu->decoder, o, f, ##args)
1076 dprintk(1, "viu/0: [%p/%d] 0x%lx/0x%lx: dma complete\n", in viu_capture_intr()
[all …]
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| D | Kconfig | 52 tristate "Freescale VIU Video Driver"
57 Support for Freescale VIU video driver. This device captures
60 Say Y here if you want to enable VIU device on MPC5121e Rev2+.
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| D | Makefile | 15 obj-$(CONFIG_VIDEO_VIU) += fsl-viu.o
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | amlogic,meson-vpu.yaml | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
29 VIU: Video Input Unit
54 tree and provides the scanout clock to the VPP and VIU.
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| /kernel/linux/linux-5.10/Documentation/admin-guide/media/ |
| D | platform-cardlist.rst | 33 fsl-viu Freescale VIU
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | meson8m2.dtsi | 78 "vencp", "vdac", "vencl", "viu", "venc", "rdma";
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| D | meson8b.dtsi | 482 "venci", "vencp", "vdac", "vencl", "viu",
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| /kernel/linux/linux-5.10/Documentation/gpu/ |
| D | meson.rst | 19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/512x/ |
| D | clock-commonclk.c | 85 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF,
886 "viu", "csb", &clkregs->sccr2, 18); in mpc512x_clk_setup_clock_tree()
1100 FOR_NODES("fsl,mpc5121-viu") { in mpc5121_clk_provide_backwards_compat()
1102 NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU); in mpc5121_clk_provide_backwards_compat()
1162 (did_register & DID_REG_VIU) ? " VIU" : "", in mpc5121_clk_provide_backwards_compat()
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mpc5121ads.dts | 115 viu@2400 {
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| D | mpc5121.dtsi | 265 viu@2400 {
266 compatible = "fsl,mpc5121-viu";
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| D | ac14xx.dts | 274 viu@2400 {
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx7ulp.c | 213 hws[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30); in imx7ulp_clk_pcc3_init()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxbb.dtsi | 735 reset-names = "viu", "venc", "vcbus", "bt656",
|