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/kernel/linux/linux-5.10/Documentation/scheduler/
D	sched-stats.rst	11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel 43 1) # of times sched_yield() was called 49 3) # of times schedule() was called 54 5) # of times try_to_wake_up() was called 55 6) # of times try_to_wake_up() was called to wake up the local cpu 78 1) # of times in this domain load_balance() was called when the 79 cpu was idle 81 the load did not require balancing when the cpu was idle 83 more tasks and failed, when the cpu was idle 85 load_balance() in this domain when the cpu was idle [all …]
D	sched-nice-design.rst	11 Unfortunately that was not that easy to implement under the old 13 support was historically coupled to timeslice length, and timeslice 14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ. 41 changing the ABI to extend priorities was discarded early on.) 48 this was long ago when hardware was weaker and caches were smaller, and 60 coupling to timeslices and granularity it was not really viable. 63 about Linux's nice level support was its assymetry around the origo 79 depend on the nice level of the parent shell - if it was at nice -10 the 80 CPU split was different than if it was at +5 or +10. 82 A third complaint against Linux's nice level support was that negative [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	41 "BriefDescription": "Cycles when a demand ifetch was pending", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … [all …]
D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f… 30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 … [all …]
D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local… [all …]
D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum… 30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu… 36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch… 42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi… 59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,… 60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p… 65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an… [all …]
D	translation.json	29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… 77 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 83 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl… [all …]
D	marked.json	35 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 47 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 107 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 119 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch co… 131 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp… 143 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict… 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i… 50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
D	frontend.json	5 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 15 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 25 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in… 40 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 50 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 55 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict… 70 …"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in th… 85 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from… 95 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
D	translation.json	15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor… 25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 75 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same… 115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t… [all …]
D	pipeline.json	25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… [all …]
D	cache.json	35 …ause the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this lo… 40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 90 …ription": "Finish stall because the NTF instruction was a load that hit on an older store and it w… 100 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 105 … "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
D	other.json	45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 50 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 55 …"BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (du… 95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d… 115 …iefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS" 145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 185 "BriefDescription": "Completion Stalled because the thread was blocked" 240 "BriefDescription": "A hwsync instruction was decoded and transferred" 255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 290 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet" [all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	10 Soon after the V4L API was added to the kernel it was criticised as too 15 another four years and two stable kernel releases until the new API was 23 1998-08-27: The :c:func:`select()` function was introduced. 27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise 39 1998-10-02: The ``id`` field was removed from 41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was 45 Codec API was released. 50 1998-11-12: The read/write directon of some ioctls was misdefined. 57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from 58 ``videodev.h`` since it was only used once in the ``videodev`` kernel [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca… 28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a … 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi… [all …]
/kernel/linux/linux-5.10/arch/arm/tools/
D	syscall.tbl	`21 # 7 was sys_waitpid 31 # 17 was sys_break 32 # 18 was sys_stat 42 # 28 was sys_fstat 45 # 31 was sys_stty 46 # 32 was sys_gtty 49 # 35 was sys_ftime 58 # 44 was sys_prof 62 # 48 was sys_signal 67 # 53 was sys_lock [all …]`
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 133 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 140 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 147 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 154 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca… 28 …"PublicDescription": "A translation entry was written into the Combined Region and Segment Table E… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi… [all …]
/kernel/linux/linux-5.10/include/uapi/linux/
D	inotify.h	30 #define IN_ACCESS 0x00000001 /* File was accessed / 31 #define IN_MODIFY 0x00000002 / File was modified / 33 #define IN_CLOSE_WRITE 0x00000008 / Writtable file was closed / 35 #define IN_OPEN 0x00000020 / File was opened / 36 #define IN_MOVED_FROM 0x00000040 / File was moved from X / 37 #define IN_MOVED_TO 0x00000080 / File was moved to Y / 38 #define IN_CREATE 0x00000100 / Subfile was created / 39 #define IN_DELETE 0x00000200 / Subfile was deleted / 40 #define IN_DELETE_SELF 0x00000400 / Self was deleted / 41 #define IN_MOVE_SELF 0x00000800 / Self was moved */ [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_zec12/
D	extended.json	21 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 28 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 35 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …A directory write to the Level-1 Data cache where the installed cache line was sourced from memory… 56 …tory write to the Level-1 Instruction cache where the installed cache line was sourced from memory… 63 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a … 105 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … [all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/cec/
D	cec-ioc-receive.rst	100 - Timestamp in ns of when the last byte of the message was transmitted. 105 - Timestamp in ns of when the last byte of the message was received. 113 filled in by the driver with the length of the reply message if ``reply`` was set. 126 the transmit result (when transmit was called in non-blocking mode). This 136 this message was received, not transmitted. 142 the payload of the reply message if ``timeout`` was set. 166 this message was transmitted, not received, unless this is the 173 this message was received, not transmitted. 245 - The message was transmitted successfully. This is mutually 248 the transmit was eventually successful. [all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/
D	tainted-kernels.rst	25 why the kernel was tainted is shown after the Process ID ('PID:') and a shortened 35 You'll find a 'Not tainted: ' there if the kernel was not tainted at the 36 time of the event; if it was, then it will print 'Tainted: ' and characters 42 the kernel got tainted earlier because a proprietary Module (``P``) was loaded, 43 a warning occurred (``W``), and an externally-built module was loaded (``O``). 61 * Proprietary module was loaded (#0) 63 * Externally-built ('out-of-tree') module was loaded (#12) 69 You can try to decode the number yourself. That's easy if there was only one 85 0 G/P 1 proprietary module was loaded 86 1 _/F 2 module was force loaded [all …]
/kernel/linux/linux-5.10/arch/sh/kernel/syscalls/
D	syscall.tbl	`27 # 17 was break 41 # 31 was stty 42 # 32 was gtty 45 # 35 was ftime 54 # 44 was prof 63 # 53 was lock 66 # 56 was mpx 68 # 58 was ulimit 69 # 59 was olduname 92 # 82 was select [all …]`
/kernel/linux/linux-5.10/arch/arm64/include/asm/
D	unistd32.h	`27 /* 7 was sys_waitpid / 39 / 13 was sys_time / 47 / 17 was sys_break / 49 / 18 was sys_stat / 57 / 22 was sys_umount / 63 / 25 was sys_stime / 67 / 27 was sys_alarm / 69 / 28 was sys_fstat / 73 / 30 was sys_utime / 75 / 31 was sys_stty */ [all …]`

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