1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL92C_PHY_COMMON_H__ 5 #define __RTL92C_PHY_COMMON_H__ 6 7 #define MAX_PRECMD_CNT 16 8 #define MAX_RFDEPENDCMD_CNT 16 9 #define MAX_POSTCMD_CNT 16 10 11 #define MAX_DOZE_WAITING_TIMES_9x 64 12 13 #define RT_CANNOT_IO(hw) false 14 #define HIGHPOWER_RADIOA_ARRAYLEN 22 15 16 #define MAX_TOLERANCE 5 17 18 #define APK_BB_REG_NUM 5 19 #define APK_AFE_REG_NUM 16 20 #define APK_CURVE_REG_NUM 4 21 #define PATH_NUM 2 22 23 #define LOOP_LIMIT 5 24 #define MAX_STALL_TIME 50 25 #define ANTENNADIVERSITYVALUE 0x80 26 #define MAX_TXPWR_IDX_NMODE_92S 63 27 #define RESET_CNT_LIMIT 3 28 29 #define IQK_ADDA_REG_NUM 16 30 #define IQK_MAC_REG_NUM 4 31 32 #define IQK_DELAY_TIME 1 33 #define RF90_PATH_MAX 2 34 35 #define CT_OFFSET_MAC_ADDR 0X16 36 37 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A 38 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 39 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66 40 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 41 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C 42 43 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F 44 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 45 46 #define CT_OFFSET_CHANNEL_PLAH 0x75 47 #define CT_OFFSET_THERMAL_METER 0x78 48 #define CT_OFFSET_RF_OPTION 0x79 49 #define CT_OFFSET_VERSION 0x7E 50 #define CT_OFFSET_CUSTOMER_ID 0x7F 51 52 #define RTL92C_MAX_PATH_NUM 2 53 #define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255 54 55 enum swchnlcmd_id { 56 CMDID_END, 57 CMDID_SET_TXPOWEROWER_LEVEL, 58 CMDID_BBREGWRITE10, 59 CMDID_WRITEPORT_ULONG, 60 CMDID_WRITEPORT_USHORT, 61 CMDID_WRITEPORT_UCHAR, 62 CMDID_RF_WRITEREG, 63 }; 64 65 struct swchnlcmd { 66 enum swchnlcmd_id cmdid; 67 u32 para1; 68 u32 para2; 69 u32 msdelay; 70 }; 71 72 enum hw90_block_e { 73 HW90_BLOCK_MAC = 0, 74 HW90_BLOCK_PHY0 = 1, 75 HW90_BLOCK_PHY1 = 2, 76 HW90_BLOCK_RF = 3, 77 HW90_BLOCK_MAXIMUM = 4, 78 }; 79 80 enum baseband_config_type { 81 BASEBAND_CONFIG_PHY_REG = 0, 82 BASEBAND_CONFIG_AGC_TAB = 1, 83 }; 84 85 enum ra_offset_area { 86 RA_OFFSET_LEGACY_OFDM1, 87 RA_OFFSET_LEGACY_OFDM2, 88 RA_OFFSET_HT_OFDM1, 89 RA_OFFSET_HT_OFDM2, 90 RA_OFFSET_HT_OFDM3, 91 RA_OFFSET_HT_OFDM4, 92 RA_OFFSET_HT_CCK, 93 }; 94 95 enum antenna_path { 96 ANTENNA_NONE, 97 ANTENNA_D, 98 ANTENNA_C, 99 ANTENNA_CD, 100 ANTENNA_B, 101 ANTENNA_BD, 102 ANTENNA_BC, 103 ANTENNA_BCD, 104 ANTENNA_A, 105 ANTENNA_AD, 106 ANTENNA_AC, 107 ANTENNA_ACD, 108 ANTENNA_AB, 109 ANTENNA_ABD, 110 ANTENNA_ABC, 111 ANTENNA_ABCD 112 }; 113 114 struct r_antenna_select_ofdm { 115 u32 r_tx_antenna:4; 116 u32 r_ant_l:4; 117 u32 r_ant_non_ht:4; 118 u32 r_ant_ht1:4; 119 u32 r_ant_ht2:4; 120 u32 r_ant_ht_s1:4; 121 u32 r_ant_non_ht_s1:4; 122 u32 ofdm_txsc:2; 123 u32 reserved:2; 124 }; 125 126 struct r_antenna_select_cck { 127 u8 r_cckrx_enable_2:2; 128 u8 r_cckrx_enable:2; 129 u8 r_ccktx_enable:4; 130 }; 131 132 struct efuse_contents { 133 u8 mac_addr[ETH_ALEN]; 134 u8 cck_tx_power_idx[6]; 135 u8 ht40_1s_tx_power_idx[6]; 136 u8 ht40_2s_tx_power_idx_diff[3]; 137 u8 ht20_tx_power_idx_diff[3]; 138 u8 ofdm_tx_power_idx_diff[3]; 139 u8 ht40_max_power_offset[3]; 140 u8 ht20_max_power_offset[3]; 141 u8 channel_plan; 142 u8 thermal_meter; 143 u8 rf_option[5]; 144 u8 version; 145 u8 oem_id; 146 u8 regulatory; 147 }; 148 149 struct tx_power_struct { 150 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 151 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 152 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 153 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 154 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 155 u8 legacy_ht_txpowerdiff; 156 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 157 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 158 u8 pwrgroup_cnt; 159 u32 mcs_original_offset[4][16]; 160 }; 161 162 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, 163 u32 regaddr, u32 bitmask); 164 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, 165 u32 regaddr, u32 bitmask, u32 data); 166 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, 167 enum radio_path rfpath, u32 regaddr, 168 u32 bitmask); 169 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw); 170 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw); 171 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw); 172 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, 173 enum radio_path rfpath); 174 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 175 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, 176 long *powerlevel); 177 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); 178 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, 179 long power_indbm); 180 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw, 181 enum nl80211_channel_type ch_type); 182 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw); 183 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw); 184 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery); 185 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, 186 u16 beaconinterval); 187 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); 188 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw); 189 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 190 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 191 enum radio_path rfpath); 192 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, 193 u32 rfpath); 194 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 195 enum rf_pwrstate rfpwr_state); 196 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw); 197 void rtl92c_phy_set_io(struct ieee80211_hw *hw); 198 void rtl92c_bb_block_on(struct ieee80211_hw *hw); 199 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask); 200 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 201 enum wireless_mode wirelessmode, 202 u8 txpwridx); 203 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw, 204 enum wireless_mode wirelessmode, 205 long power_indbm); 206 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 207 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw); 208 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 209 u8 channel, u8 *stage, u8 *step, 210 u32 *delay); 211 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw); 212 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, 213 enum radio_path rfpath, u32 offset); 214 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw, 215 enum radio_path rfpath, u32 offset, 216 u32 data); 217 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, 218 enum radio_path rfpath, u32 offset); 219 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, 220 enum radio_path rfpath, u32 offset, 221 u32 data); 222 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 223 void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 224 u32 regaddr, u32 bitmask, 225 u32 data); 226 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 227 228 #endif 229