1synopsys DWC3 CORE 2 3DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 4 as described in 'usb/generic.txt' 5 6Required properties: 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: list of clock names. Ideally should be "ref", 11 "bus_early", "suspend" but may be less or more. 12 - clocks: list of phandle and clock specifier pairs corresponding to 13 entries in the clock-names property. 14 15Exception for clocks: 16 clocks are optional if the parent node (i.e. glue-layer) is compatible to 17 one of the following: 18 "cavium,octeon-7130-usb-uctl" 19 "qcom,dwc3" 20 "samsung,exynos5250-dwusb3" 21 "samsung,exynos5433-dwusb3" 22 "samsung,exynos7-dwusb3" 23 "sprd,sc9860-dwc3" 24 "st,stih407-dwc3" 25 "ti,am437x-dwc3" 26 "ti,dwc3" 27 "ti,keystone-dwc3" 28 "rockchip,rk3399-dwc3" 29 "xlnx,zynqmp-dwc3" 30 31Optional properties: 32 - usb-phy : array of phandle for the PHY device. The first element 33 in the array is expected to be a handle to the USB2/HS PHY and 34 the second element is expected to be a handle to the USB3/SS PHY 35 - phys: from the *Generic PHY* bindings 36 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" 37 or "usb3-phy". 38 - resets: set of phandle and reset specifier pairs 39 - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM 40 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable 41 - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command 42 failure SW work-around for DWC_usb31 version 1.70a-ea06 43 and prior. 44 - snps,disable_scramble_quirk: true when SW should disable data scrambling. 45 Only really useful for FPGA builds. 46 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled 47 - snps,lpm-nyet-threshold: LPM NYET threshold 48 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk 49 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 50 - snps,req_p1p2p3_quirk: when set, the core will always request for 51 P1/P2/P3 transition sequence. 52 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain 53 amount of 8B10B errors occur. 54 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change 55 from P0 to P1/P2/P3. 56 - snps,lfps_filter_quirk: when set core will filter LFPS reception. 57 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start 58 Polling LFPS after RX.Detect. 59 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value. 60 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the 61 LTSSM during USB3 Compliance mode. 62 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy. 63 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy. 64 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG, 65 disabling the suspend signal to the PHY. 66 - snps,dis-u1-entry-quirk: set if link entering into U1 needs to be disabled. 67 - snps,dis-u2-entry-quirk: set if link entering into U2 needs to be disabled. 68 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection 69 in PHY P3 power state. 70 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists 71 in GUSB2PHYCFG, specify that USB2 PHY doesn't provide 72 a free-running PHY clock. 73 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power 74 from P0 to P1/P2/P3 without delay. 75 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check 76 during HS transmit. 77 - snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in 78 park mode are disabled. 79 - snps,dis_metastability_quirk: when set, disable metastability workaround. 80 CAUTION: use only if you are absolutely sure of it. 81 - snps,dis-split-quirk: when set, change the way URBs are handled by the 82 driver. Needed to avoid -EPROTO errors with usbhid 83 on some devices (Hikey 970). 84 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal 85 utmi_l1_suspend_n, false when asserts utmi_sleep_n 86 - snps,hird-threshold: HIRD threshold 87 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for 88 UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. 89 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ 90 register for post-silicon frame length adjustment when the 91 fladj_30mhz_sdbnd signal is invalid or incorrect. 92 - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode 93 only. Set this and rx-max-burst-prd to a valid, 94 non-zero value 1-16 (DWC_usb31 programming guide 95 section 1.2.4) to enable periodic ESS RX threshold. 96 - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set 97 this and rx-thr-num-pkt-prd to a valid, non-zero value 98 1-16 (DWC_usb31 programming guide section 1.2.4) to 99 enable periodic ESS RX threshold. 100 - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode 101 only. Set this and tx-max-burst-prd to a valid, 102 non-zero value 1-16 (DWC_usb31 programming guide 103 section 1.2.3) to enable periodic ESS TX threshold. 104 - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set 105 this and tx-thr-num-pkt-prd to a valid, non-zero value 106 1-16 (DWC_usb31 programming guide section 1.2.3) to 107 enable periodic ESS TX threshold. 108 109 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. 110 - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 111 register, undefined length INCR burst type enable and INCRx type. 112 When just one value, which means INCRX burst mode enabled. When 113 more than one value, which means undefined length INCR burst type 114 enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. 115 116 - in addition all properties from usb-xhci.txt from the current directory are 117 supported as well 118 119 120This is usually a subnode to DWC3 glue to which it is connected. 121 122dwc3@4a030000 { 123 compatible = "snps,dwc3"; 124 reg = <0x4a030000 0xcfff>; 125 interrupts = <0 92 4> 126 usb-phy = <&usb2_phy>, <&usb3,phy>; 127 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 128}; 129