1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_state.h"
36
37 #include "fd3_context.h"
38 #include "fd3_emit.h"
39 #include "fd3_format.h"
40 #include "fd3_gmem.h"
41 #include "fd3_program.h"
42 #include "fd3_zsa.h"
43
44 static void
fd3_gmem_emit_set_prog(struct fd_context * ctx,struct fd3_emit * emit,struct fd_program_stateobj * prog)45 fd3_gmem_emit_set_prog(struct fd_context *ctx, struct fd3_emit *emit,
46 struct fd_program_stateobj *prog)
47 {
48 emit->skip_consts = true;
49 emit->key.vs = prog->vs;
50 emit->key.fs = prog->fs;
51 emit->prog = fd3_program_state(
52 ir3_cache_lookup(ctx->shader_cache, &emit->key, &ctx->debug));
53 /* reset the fd3_emit_get_*p cache */
54 emit->vs = NULL;
55 emit->fs = NULL;
56 }
57
58 static void
emit_mrt(struct fd_ringbuffer * ring,unsigned nr_bufs,struct pipe_surface ** bufs,const uint32_t * bases,uint32_t bin_w,bool decode_srgb)59 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
60 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
61 bool decode_srgb)
62 {
63 enum a3xx_tile_mode tile_mode;
64 unsigned i;
65
66 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
67 enum pipe_format pformat = 0;
68 enum a3xx_color_fmt format = 0;
69 enum a3xx_color_swap swap = WZYX;
70 bool srgb = false;
71 struct fd_resource *rsc = NULL;
72 uint32_t stride = 0;
73 uint32_t base = 0;
74 uint32_t offset = 0;
75
76 if (bin_w) {
77 tile_mode = TILE_32X32;
78 } else {
79 tile_mode = LINEAR;
80 }
81
82 if ((i < nr_bufs) && bufs[i]) {
83 struct pipe_surface *psurf = bufs[i];
84
85 rsc = fd_resource(psurf->texture);
86 pformat = psurf->format;
87 /* In case we're drawing to Z32F_S8, the "color" actually goes to
88 * the stencil
89 */
90 if (rsc->stencil) {
91 rsc = rsc->stencil;
92 pformat = rsc->b.b.format;
93 if (bases)
94 bases++;
95 }
96 format = fd3_pipe2color(pformat);
97 if (decode_srgb)
98 srgb = util_format_is_srgb(pformat);
99 else
100 pformat = util_format_linear(pformat);
101
102 assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
103
104 offset = fd_resource_offset(rsc, psurf->u.tex.level,
105 psurf->u.tex.first_layer);
106 swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
107
108 if (bin_w) {
109 stride = bin_w << fdl_cpp_shift(&rsc->layout);
110
111 if (bases) {
112 base = bases[i];
113 }
114 } else {
115 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
116 tile_mode = rsc->layout.tile_mode;
117 }
118 } else if (i < nr_bufs && bases) {
119 base = bases[i];
120 }
121
122 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
123 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
124 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
125 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
126 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
127 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
128 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
129 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
130 } else {
131 OUT_RELOC(ring, rsc->bo, offset, 0, -1);
132 }
133
134 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
135 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
136 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
137 fd3_fs_output_format(pformat))));
138 }
139 }
140
141 static bool
use_hw_binning(struct fd_batch * batch)142 use_hw_binning(struct fd_batch *batch)
143 {
144 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
145
146 /* workaround: combining scissor optimization and hw binning
147 * seems problematic. Seems like we end up with a mismatch
148 * between binning pass and rendering pass, wrt. where the hw
149 * thinks the vertices belong. And the blob driver doesn't
150 * seem to implement anything like scissor optimization, so
151 * not entirely sure what I might be missing.
152 *
153 * But scissor optimization is mainly for window managers,
154 * which don't have many vertices (and therefore doesn't
155 * benefit much from binning pass).
156 *
157 * So for now just disable binning if scissor optimization is
158 * used.
159 */
160 if (gmem->minx || gmem->miny)
161 return false;
162
163 if ((gmem->maxpw * gmem->maxph) > 32)
164 return false;
165
166 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
167 return false;
168
169 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
170 }
171
172 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
173 static void update_vsc_pipe(struct fd_batch *batch);
174 static void
emit_binning_workaround(struct fd_batch * batch)175 emit_binning_workaround(struct fd_batch *batch) assert_dt
176 {
177 struct fd_context *ctx = batch->ctx;
178 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
179 struct fd_ringbuffer *ring = batch->gmem;
180 struct fd3_emit emit = {
181 .debug = &ctx->debug,
182 .vtx = &ctx->solid_vbuf_state,
183 .key =
184 {
185 .vs = ctx->solid_prog.vs,
186 .fs = ctx->solid_prog.fs,
187 },
188 };
189
190 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->solid_prog);
191
192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
193 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
194 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
195 A3XX_RB_MODE_CONTROL_MRT(0));
196 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
197 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
198 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
199
200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
201 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
202 A3XX_RB_COPY_CONTROL_MODE(0) |
203 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
204 OUT_RELOC(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0,
205 -1); /* RB_COPY_DEST_BASE */
206 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
207 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
208 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
209 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
210 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
211 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
212
213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
214 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
215 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
216 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
217
218 fd3_program_emit(ring, &emit, 0, NULL);
219 fd3_emit_vertex_bufs(ring, &emit);
220
221 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
222 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
223 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
224 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
225 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
226 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
227 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
228 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
229 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
230
231 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
232 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
233 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
234
235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
236 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
237 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
238 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
239
240 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
241 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
242
243 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
244 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
245 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
246 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
247 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
248 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
249 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
250 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
251 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
252
253 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
254 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0f));
255
256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
257 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
258 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
259 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
260 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
261
262 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
263 OUT_RING(ring,
264 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
265 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
266 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
267 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
268
269 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
270 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
271 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
272 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
273 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
274
275 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
276 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
277 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
278 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
279 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
280
281 fd_wfi(batch, ring);
282 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
283 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0f));
284 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0f));
285 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0f));
286 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0f));
287 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
288 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
289
290 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
291 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
292 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
293 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
294 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
295 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
296
297 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
298 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
299 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
300
301 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
302 OUT_RING(ring, 0x00000000); /* viz query info. */
303 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE, INDEX_SIZE_32_BIT,
304 IGNORE_VISIBILITY, 0));
305 OUT_RING(ring, 2); /* NumIndices */
306 OUT_RING(ring, 2);
307 OUT_RING(ring, 1);
308 fd_reset_wfi(batch);
309
310 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
311 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
312
313 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
314 OUT_RING(ring, 0x00000000);
315
316 fd_wfi(batch, ring);
317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
318 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
319 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
320
321 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
322 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
323 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
324 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
325
326 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
327 OUT_RING(ring, 0x00000000);
328 }
329
330 /* transfer from gmem to system memory (ie. normal RAM) */
331
332 static void
emit_gmem2mem_surf(struct fd_batch * batch,enum adreno_rb_copy_control_mode mode,bool stencil,uint32_t base,struct pipe_surface * psurf)333 emit_gmem2mem_surf(struct fd_batch *batch,
334 enum adreno_rb_copy_control_mode mode, bool stencil,
335 uint32_t base, struct pipe_surface *psurf)
336 {
337 struct fd_ringbuffer *ring = batch->gmem;
338 struct fd_resource *rsc = fd_resource(psurf->texture);
339 enum pipe_format format = psurf->format;
340
341 if (!rsc->valid)
342 return;
343
344 if (stencil) {
345 rsc = rsc->stencil;
346 format = rsc->b.b.format;
347 }
348
349 uint32_t offset =
350 fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
351 uint32_t pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
352
353 assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
354
355 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
356 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
357 A3XX_RB_COPY_CONTROL_MODE(mode) |
358 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
359 COND(format == PIPE_FORMAT_Z32_FLOAT ||
360 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
361 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
362
363 OUT_RELOC(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
364 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(pitch));
365 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
366 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
367 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
368 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
369 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
370
371 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
372 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
373 }
374
375 static void
fd3_emit_tile_gmem2mem(struct fd_batch * batch,const struct fd_tile * tile)376 fd3_emit_tile_gmem2mem(struct fd_batch *batch,
377 const struct fd_tile *tile) assert_dt
378 {
379 struct fd_context *ctx = batch->ctx;
380 struct fd_ringbuffer *ring = batch->gmem;
381 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
382 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
383 struct fd3_emit emit = {.debug = &ctx->debug,
384 .vtx = &ctx->solid_vbuf_state,
385 .key = {
386 .vs = ctx->solid_prog.vs,
387 .fs = ctx->solid_prog.fs,
388 }};
389 int i;
390
391 emit.prog = fd3_program_state(
392 ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
393
394 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
395 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
396
397 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
398 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
399 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
400 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
401 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
402 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
403 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
404 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
405 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
406
407 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
408 OUT_RING(ring, 0xff000000 | A3XX_RB_STENCILREFMASK_STENCILREF(0) |
409 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
410 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
411 OUT_RING(ring, 0xff000000 | A3XX_RB_STENCILREFMASK_STENCILREF(0) |
412 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
413 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
414
415 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
416 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
417
418 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
419 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
420
421 fd_wfi(batch, ring);
422 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
423 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width / 2.0f - 0.5f));
424 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width / 2.0f));
425 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height / 2.0f - 0.5f));
426 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height / 2.0f));
427 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
428 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
429
430 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
431 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
432 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
433 A3XX_RB_MODE_CONTROL_MRT(0));
434
435 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
436 OUT_RING(ring,
437 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
438 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
439 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
440 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
441
442 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
443 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
444 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
445 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
446
447 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
448 OUT_RING(ring,
449 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
450 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
451 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
452 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
453
454 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
455 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
456 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
457 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
458 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
459
460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
461 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
462 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
463 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
464 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
465
466 fd3_program_emit(ring, &emit, 0, NULL);
467 fd3_emit_vertex_bufs(ring, &emit);
468
469 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
470 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
471 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
472 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
473 gmem->zsbuf_base[0], pfb->zsbuf);
474 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
475 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
476 gmem->zsbuf_base[1], pfb->zsbuf);
477 }
478
479 if (batch->resolve & FD_BUFFER_COLOR) {
480 for (i = 0; i < pfb->nr_cbufs; i++) {
481 if (!pfb->cbufs[i])
482 continue;
483 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
484 continue;
485 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false, gmem->cbuf_base[i],
486 pfb->cbufs[i]);
487 }
488 }
489
490 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
491 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
492 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
493 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
494
495 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
496 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
497 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
498 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
499 }
500
501 /* transfer from system memory to gmem */
502
503 static void
emit_mem2gmem_surf(struct fd_batch * batch,const uint32_t bases[],struct pipe_surface ** psurf,uint32_t bufs,uint32_t bin_w)504 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
505 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
506 {
507 struct fd_ringbuffer *ring = batch->gmem;
508 struct pipe_surface *zsbufs[2];
509
510 assert(bufs > 0);
511
512 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
513 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
514 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
515 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
516
517 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
518
519 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
520 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
521 /* Depth is stored as unorm in gmem, so we have to write it in using a
522 * special blit shader which writes depth.
523 */
524 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
525 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
526 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
527 A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE |
528 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
529 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
530
531 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
532 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
533 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
534 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
535
536 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
537 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
538 OUT_RING(ring, 0);
539 } else {
540 /* The gmem_restore_tex logic will put the first buffer's stencil
541 * as color. Supply it with the proper information to make that
542 * happen.
543 */
544 zsbufs[0] = zsbufs[1] = psurf[0];
545 psurf = zsbufs;
546 bufs = 2;
547 }
548 } else {
549 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
550 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
551 }
552
553 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
554
555 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
556 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
557 }
558
559 static void
fd3_emit_tile_mem2gmem(struct fd_batch * batch,const struct fd_tile * tile)560 fd3_emit_tile_mem2gmem(struct fd_batch *batch,
561 const struct fd_tile *tile) assert_dt
562 {
563 struct fd_context *ctx = batch->ctx;
564 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
565 struct fd_ringbuffer *ring = batch->gmem;
566 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
567 struct fd3_emit emit = {
568 .debug = &ctx->debug,
569 .vtx = &ctx->blit_vbuf_state,
570 .sprite_coord_enable = 1,
571 };
572 /* NOTE: They all use the same VP, this is for vtx bufs. */
573 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[0]);
574
575 float x0, y0, x1, y1;
576 unsigned bin_w = tile->bin_w;
577 unsigned bin_h = tile->bin_h;
578 unsigned i;
579
580 /* write texture coordinates to vertexbuf: */
581 x0 = ((float)tile->xoff) / ((float)pfb->width);
582 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
583 y0 = ((float)tile->yoff) / ((float)pfb->height);
584 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
585
586 OUT_PKT3(ring, CP_MEM_WRITE, 5);
587 OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
588 OUT_RING(ring, fui(x0));
589 OUT_RING(ring, fui(y0));
590 OUT_RING(ring, fui(x1));
591 OUT_RING(ring, fui(y1));
592
593 fd3_emit_cache_flush(batch, ring);
594
595 for (i = 0; i < 4; i++) {
596 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
597 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
598 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
599 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
600
601 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
602 OUT_RING(
603 ring,
604 A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
605 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
606 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
607 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
608 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
609 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
610 }
611
612 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
613 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
614 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
615
616 fd_wfi(batch, ring);
617 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
618 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
619
620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
621 OUT_RING(ring, 0);
622 OUT_RING(ring, 0);
623
624 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
625 OUT_RING(ring,
626 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
627
628 fd_wfi(batch, ring);
629 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
630 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w / 2.0f - 0.5f));
631 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w / 2.0f));
632 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h / 2.0f - 0.5f));
633 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h / 2.0f));
634 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
635 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
636
637 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
638 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
639 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
640 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
641 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
642
643 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
644 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
645 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
646 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
647 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
648
649 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
650 OUT_RING(ring, 0x2 | A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
651 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
652 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
653 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
654 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
655 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
656 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
657 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
658
659 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
660 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
661 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
662
663 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
664 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
665 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
666 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
667
668 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
669 OUT_RING(ring,
670 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
671 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
672 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
673 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
674
675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
676 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
677 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
678 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
679 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
680
681 fd3_emit_vertex_bufs(ring, &emit);
682
683 /* for gmem pitch/base calculations, we need to use the non-
684 * truncated tile sizes:
685 */
686 bin_w = gmem->bin_w;
687 bin_h = gmem->bin_h;
688
689 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
690 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[pfb->nr_cbufs - 1]);
691 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
692 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs,
693 bin_w);
694 }
695
696 if (fd_gmem_needs_restore(batch, tile,
697 FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
698 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
699 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
700 /* Non-float can use a regular color write. It's split over 8-bit
701 * components, so half precision is always sufficient.
702 */
703 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[0]);
704 } else {
705 /* Float depth needs special blit shader that writes depth */
706 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
707 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->blit_z);
708 else
709 fd3_gmem_emit_set_prog(ctx, &emit, &ctx->blit_zs);
710 }
711 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
712 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
713 }
714
715 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
716 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
717 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
718 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
719
720 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
721 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
722 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
723 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
724 }
725
726 static void
patch_draws(struct fd_batch * batch,enum pc_di_vis_cull_mode vismode)727 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
728 {
729 unsigned i;
730 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
731 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
732 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
733 }
734 util_dynarray_clear(&batch->draw_patches);
735 }
736
737 static void
patch_rbrc(struct fd_batch * batch,uint32_t val)738 patch_rbrc(struct fd_batch *batch, uint32_t val)
739 {
740 unsigned i;
741 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
742 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
743 *patch->cs = patch->val | val;
744 }
745 util_dynarray_clear(&batch->rbrc_patches);
746 }
747
748 /* for rendering directly to system memory: */
749 static void
fd3_emit_sysmem_prep(struct fd_batch * batch)750 fd3_emit_sysmem_prep(struct fd_batch *batch) assert_dt
751 {
752 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
753 struct fd_ringbuffer *ring = batch->gmem;
754 uint32_t i, pitch = 0;
755
756 for (i = 0; i < pfb->nr_cbufs; i++) {
757 struct pipe_surface *psurf = pfb->cbufs[i];
758 if (!psurf)
759 continue;
760 struct fd_resource *rsc = fd_resource(psurf->texture);
761 pitch = fd_resource_pitch(rsc, psurf->u.tex.level) / rsc->layout.cpp;
762 }
763
764 fd3_emit_restore(batch, ring);
765
766 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
767 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
768 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
769
770 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
771
772 /* setup scissor/offset for current tile: */
773 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
774 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) | A3XX_RB_WINDOW_OFFSET_Y(0));
775
776 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
777 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
778 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
779 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
780 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
781
782 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
783 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
784 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
785 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
786 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
787
788 patch_draws(batch, IGNORE_VISIBILITY);
789 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
790 }
791
792 static void
update_vsc_pipe(struct fd_batch * batch)793 update_vsc_pipe(struct fd_batch *batch) assert_dt
794 {
795 struct fd_context *ctx = batch->ctx;
796 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
797 struct fd3_context *fd3_ctx = fd3_context(ctx);
798 struct fd_ringbuffer *ring = batch->gmem;
799 int i;
800
801 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
802 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
803
804 for (i = 0; i < 8; i++) {
805 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
806
807 if (!ctx->vsc_pipe_bo[i]) {
808 ctx->vsc_pipe_bo[i] = fd_bo_new(
809 ctx->dev, 0x40000, 0, "vsc_pipe[%u]", i);
810 }
811
812 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
813 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
814 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
815 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
816 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
817 OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0,
818 0); /* VSC_PIPE[i].DATA_ADDRESS */
819 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) -
820 32); /* VSC_PIPE[i].DATA_LENGTH */
821 }
822 }
823
824 static void
emit_binning_pass(struct fd_batch * batch)825 emit_binning_pass(struct fd_batch *batch) assert_dt
826 {
827 struct fd_context *ctx = batch->ctx;
828 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
829 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
830 struct fd_ringbuffer *ring = batch->gmem;
831 int i;
832
833 uint32_t x1 = gmem->minx;
834 uint32_t y1 = gmem->miny;
835 uint32_t x2 = gmem->minx + gmem->width - 1;
836 uint32_t y2 = gmem->miny + gmem->height - 1;
837
838 if (ctx->screen->gpu_id == 320) {
839 emit_binning_workaround(batch);
840 fd_wfi(batch, ring);
841 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
842 OUT_RING(ring, 0x00007fff);
843 }
844
845 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
846 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
847
848 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
849 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
850 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
851 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
852
853 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
854 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
855 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
856
857 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
858 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
859 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
860 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
861
862 /* setup scissor/offset for whole screen: */
863 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
864 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) | A3XX_RB_WINDOW_OFFSET_Y(y1));
865
866 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
867 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
868
869 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
870 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
871 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
872 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
873 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
874
875 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
876 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
877 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
878 A3XX_RB_MODE_CONTROL_MRT(0));
879
880 for (i = 0; i < 4; i++) {
881 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
882 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
883 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
884 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
885 }
886
887 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
888 OUT_RING(ring,
889 A3XX_PC_VSTREAM_CONTROL_SIZE(1) | A3XX_PC_VSTREAM_CONTROL_N(0));
890
891 /* emit IB to binning drawcmds: */
892 fd3_emit_ib(ring, batch->binning);
893 fd_reset_wfi(batch);
894
895 fd_wfi(batch, ring);
896
897 /* and then put stuff back the way it was: */
898
899 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
900 OUT_RING(ring, 0x00000000);
901
902 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
903 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
904 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
905 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
906 A3XX_SP_SP_CTRL_REG_L0MODE(0));
907
908 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
909 OUT_RING(ring, 0x00000000);
910
911 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
912 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
913 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
914 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
915
916 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
917 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
918 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
919 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
920 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
921 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
922 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
923
924 fd_event_write(batch, ring, CACHE_FLUSH);
925 fd_wfi(batch, ring);
926
927 if (ctx->screen->gpu_id == 320) {
928 /* dummy-draw workaround: */
929 OUT_PKT3(ring, CP_DRAW_INDX, 3);
930 OUT_RING(ring, 0x00000000);
931 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, INDEX_SIZE_IGN,
932 IGNORE_VISIBILITY, 0));
933 OUT_RING(ring, 0); /* NumIndices */
934 fd_reset_wfi(batch);
935 }
936
937 OUT_PKT3(ring, CP_NOP, 4);
938 OUT_RING(ring, 0x00000000);
939 OUT_RING(ring, 0x00000000);
940 OUT_RING(ring, 0x00000000);
941 OUT_RING(ring, 0x00000000);
942
943 fd_wfi(batch, ring);
944
945 if (ctx->screen->gpu_id == 320) {
946 emit_binning_workaround(batch);
947 }
948 }
949
950 /* before first tile */
951 static void
fd3_emit_tile_init(struct fd_batch * batch)952 fd3_emit_tile_init(struct fd_batch *batch) assert_dt
953 {
954 struct fd_ringbuffer *ring = batch->gmem;
955 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
956 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
957 uint32_t rb_render_control;
958
959 fd3_emit_restore(batch, ring);
960
961 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
962 * at the right and bottom edge tiles
963 */
964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
965 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
966 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
967
968 update_vsc_pipe(batch);
969
970 fd_wfi(batch, ring);
971 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
972 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
973 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
974
975 if (use_hw_binning(batch)) {
976 /* emit hw binning pass: */
977 emit_binning_pass(batch);
978
979 patch_draws(batch, USE_VISIBILITY);
980 } else {
981 patch_draws(batch, IGNORE_VISIBILITY);
982 }
983
984 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
985 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
986
987 patch_rbrc(batch, rb_render_control);
988 }
989
990 /* before mem2gmem */
991 static void
fd3_emit_tile_prep(struct fd_batch * batch,const struct fd_tile * tile)992 fd3_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
993 {
994 struct fd_ringbuffer *ring = batch->gmem;
995 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
996
997 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
998 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
999 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
1000 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
1001 }
1002
1003 /* before IB to rendering cmds: */
1004 static void
fd3_emit_tile_renderprep(struct fd_batch * batch,const struct fd_tile * tile)1005 fd3_emit_tile_renderprep(struct fd_batch *batch,
1006 const struct fd_tile *tile) assert_dt
1007 {
1008 struct fd_context *ctx = batch->ctx;
1009 struct fd3_context *fd3_ctx = fd3_context(ctx);
1010 struct fd_ringbuffer *ring = batch->gmem;
1011 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1012 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1013
1014 uint32_t x1 = tile->xoff;
1015 uint32_t y1 = tile->yoff;
1016 uint32_t x2 = tile->xoff + tile->bin_w - 1;
1017 uint32_t y2 = tile->yoff + tile->bin_h - 1;
1018
1019 uint32_t reg;
1020
1021 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
1022 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
1023 if (pfb->zsbuf) {
1024 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
1025 }
1026 OUT_RING(ring, reg);
1027 if (pfb->zsbuf) {
1028 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1029 OUT_RING(ring,
1030 A3XX_RB_DEPTH_PITCH(gmem->bin_w << fdl_cpp_shift(&rsc->layout)));
1031 if (rsc->stencil) {
1032 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1033 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1034 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(gmem->bin_w << fdl_cpp_shift(
1035 &rsc->stencil->layout)));
1036 }
1037 } else {
1038 OUT_RING(ring, 0x00000000);
1039 }
1040
1041 if (use_hw_binning(batch)) {
1042 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
1043 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
1044
1045 assert(pipe->w && pipe->h);
1046
1047 fd_event_write(batch, ring, HLSQ_FLUSH);
1048 fd_wfi(batch, ring);
1049
1050 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1051 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1052 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1053
1054 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1055 OUT_RELOC(ring, pipe_bo, 0, 0,
1056 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1057 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <-
1058 VSC_SIZE_ADDRESS + (p * 4) */
1059 (tile->p * 4), 0, 0);
1060 } else {
1061 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1062 OUT_RING(ring, 0x00000000);
1063 }
1064
1065 OUT_PKT3(ring, CP_SET_BIN, 3);
1066 OUT_RING(ring, 0x00000000);
1067 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1068 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1069
1070 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w,
1071 true);
1072
1073 /* setup scissor/offset for current tile: */
1074 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1075 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1076 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1077
1078 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1079 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1080 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1081 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1082 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1083 }
1084
1085 void
fd3_gmem_init(struct pipe_context * pctx)1086 fd3_gmem_init(struct pipe_context *pctx) disable_thread_safety_analysis
1087 {
1088 struct fd_context *ctx = fd_context(pctx);
1089
1090 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1091 ctx->emit_tile_init = fd3_emit_tile_init;
1092 ctx->emit_tile_prep = fd3_emit_tile_prep;
1093 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1094 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1095 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1096 }
1097