1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_HEATHROW_H 3 #define _ASM_POWERPC_HEATHROW_H 4 #ifdef __KERNEL__ 5 /* 6 * heathrow.h: definitions for using the "Heathrow" I/O controller chip. 7 * 8 * Grabbed from Open Firmware definitions on a PowerBook G3 Series 9 * 10 * Copyright (C) 1997 Paul Mackerras. 11 */ 12 13 /* Front light color on Yikes/B&W G3. 32 bits */ 14 #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */ 15 16 /* Brightness/contrast (gossamer iMac ?). 8 bits */ 17 #define HEATHROW_BRIGHTNESS_CNTL 0x32 18 #define HEATHROW_CONTRAST_CNTL 0x33 19 20 /* offset from ohare base for feature control register */ 21 #define HEATHROW_MBCR 0x34 /* Media bay control */ 22 #define HEATHROW_FCR 0x38 /* Feature control */ 23 #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ 24 25 /* 26 * Bits in feature control register. 27 * Bits postfixed with a _N are in inverse logic 28 */ 29 #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */ 30 #define HRW_BAY_POWER_N 0x00000002 31 #define HRW_BAY_PCI_ENABLE 0x00000004 32 #define HRW_BAY_IDE_ENABLE 0x00000008 33 #define HRW_BAY_FLOPPY_ENABLE 0x00000010 34 #define HRW_IDE0_ENABLE 0x00000020 35 #define HRW_IDE0_RESET_N 0x00000040 36 #define HRW_BAY_DEV_MASK 0x0000001c 37 #define HRW_BAY_RESET_N 0x00000080 38 #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ 39 #define HRW_SCC_ENABLE 0x00000200 40 #define HRW_MESH_ENABLE 0x00000400 41 #define HRW_SWIM_ENABLE 0x00000800 42 #define HRW_SOUND_POWER_N 0x00001000 43 #define HRW_SOUND_CLK_ENABLE 0x00002000 44 #define HRW_SCCA_IO 0x00004000 45 #define HRW_SCCB_IO 0x00008000 46 #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */ 47 #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */ 48 #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */ 49 #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ 50 #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ 51 #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ 52 #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ 53 #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ 54 #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ 55 #define HRW_RESET_SCC 0x02000000 56 #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */ 57 #define HRW_USE_MFDC 0x08000000 /* ??? (0) */ 58 #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ 59 #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ 60 61 /* We OR those features at boot on desktop G3s */ 62 #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) 63 64 /* Looks like Heathrow has some sort of GPIOs as well... */ 65 #define HRW_GPIO_MODEM_RESET 0x6d 66 67 #endif /* __KERNEL__ */ 68 #endif /* _ASM_POWERPC_HEATHROW_H */ 69