1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5420 SoC device tree source 4 * 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung Exynos5420 SoC device nodes are listed in this file. 9 * Exynos5420 based board files can include this file and provide 10 * values for board specfic bindings. 11 */ 12 13#include "exynos54xx.dtsi" 14#include <dt-bindings/clock/exynos5420.h> 15#include <dt-bindings/clock/exynos-audss-clk.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17 18/ { 19 compatible = "samsung,exynos5420", "samsung,exynos5"; 20 21 aliases { 22 mshc0 = &mmc_0; 23 mshc1 = &mmc_1; 24 mshc2 = &mmc_2; 25 pinctrl0 = &pinctrl_0; 26 pinctrl1 = &pinctrl_1; 27 pinctrl2 = &pinctrl_2; 28 pinctrl3 = &pinctrl_3; 29 pinctrl4 = &pinctrl_4; 30 i2c8 = &hsi2c_8; 31 i2c9 = &hsi2c_9; 32 i2c10 = &hsi2c_10; 33 gsc0 = &gsc_0; 34 gsc1 = &gsc_1; 35 spi0 = &spi_0; 36 spi1 = &spi_1; 37 spi2 = &spi_2; 38 }; 39 40 /* 41 * The 'cpus' node is not present here but instead it is provided 42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 43 */ 44 45 cluster_a15_opp_table: opp_table0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-1800000000 { 50 opp-hz = /bits/ 64 <1800000000>; 51 opp-microvolt = <1250000 1250000 1500000>; 52 clock-latency-ns = <140000>; 53 }; 54 opp-1700000000 { 55 opp-hz = /bits/ 64 <1700000000>; 56 opp-microvolt = <1212500 1212500 1500000>; 57 clock-latency-ns = <140000>; 58 }; 59 opp-1600000000 { 60 opp-hz = /bits/ 64 <1600000000>; 61 opp-microvolt = <1175000 1175000 1500000>; 62 clock-latency-ns = <140000>; 63 }; 64 opp-1500000000 { 65 opp-hz = /bits/ 64 <1500000000>; 66 opp-microvolt = <1137500 1137500 1500000>; 67 clock-latency-ns = <140000>; 68 }; 69 opp-1400000000 { 70 opp-hz = /bits/ 64 <1400000000>; 71 opp-microvolt = <1112500 1112500 1500000>; 72 clock-latency-ns = <140000>; 73 }; 74 opp-1300000000 { 75 opp-hz = /bits/ 64 <1300000000>; 76 opp-microvolt = <1062500 1062500 1500000>; 77 clock-latency-ns = <140000>; 78 }; 79 opp-1200000000 { 80 opp-hz = /bits/ 64 <1200000000>; 81 opp-microvolt = <1037500 1037500 1500000>; 82 clock-latency-ns = <140000>; 83 }; 84 opp-1100000000 { 85 opp-hz = /bits/ 64 <1100000000>; 86 opp-microvolt = <1012500 1012500 1500000>; 87 clock-latency-ns = <140000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = < 987500 987500 1500000>; 92 clock-latency-ns = <140000>; 93 }; 94 opp-900000000 { 95 opp-hz = /bits/ 64 <900000000>; 96 opp-microvolt = < 962500 962500 1500000>; 97 clock-latency-ns = <140000>; 98 }; 99 opp-800000000 { 100 opp-hz = /bits/ 64 <800000000>; 101 opp-microvolt = < 937500 937500 1500000>; 102 clock-latency-ns = <140000>; 103 }; 104 opp-700000000 { 105 opp-hz = /bits/ 64 <700000000>; 106 opp-microvolt = < 912500 912500 1500000>; 107 clock-latency-ns = <140000>; 108 }; 109 }; 110 111 cluster_a7_opp_table: opp_table1 { 112 compatible = "operating-points-v2"; 113 opp-shared; 114 115 opp-1300000000 { 116 opp-hz = /bits/ 64 <1300000000>; 117 opp-microvolt = <1275000>; 118 clock-latency-ns = <140000>; 119 }; 120 opp-1200000000 { 121 opp-hz = /bits/ 64 <1200000000>; 122 opp-microvolt = <1212500>; 123 clock-latency-ns = <140000>; 124 }; 125 opp-1100000000 { 126 opp-hz = /bits/ 64 <1100000000>; 127 opp-microvolt = <1162500>; 128 clock-latency-ns = <140000>; 129 }; 130 opp-1000000000 { 131 opp-hz = /bits/ 64 <1000000000>; 132 opp-microvolt = <1112500>; 133 clock-latency-ns = <140000>; 134 }; 135 opp-900000000 { 136 opp-hz = /bits/ 64 <900000000>; 137 opp-microvolt = <1062500>; 138 clock-latency-ns = <140000>; 139 }; 140 opp-800000000 { 141 opp-hz = /bits/ 64 <800000000>; 142 opp-microvolt = <1025000>; 143 clock-latency-ns = <140000>; 144 }; 145 opp-700000000 { 146 opp-hz = /bits/ 64 <700000000>; 147 opp-microvolt = <975000>; 148 clock-latency-ns = <140000>; 149 }; 150 opp-600000000 { 151 opp-hz = /bits/ 64 <600000000>; 152 opp-microvolt = <937500>; 153 clock-latency-ns = <140000>; 154 }; 155 }; 156 157 soc: soc { 158 cci: cci@10d20000 { 159 compatible = "arm,cci-400"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 reg = <0x10d20000 0x1000>; 163 ranges = <0x0 0x10d20000 0x6000>; 164 165 cci_control0: slave-if@4000 { 166 compatible = "arm,cci-400-ctrl-if"; 167 interface-type = "ace"; 168 reg = <0x4000 0x1000>; 169 }; 170 cci_control1: slave-if@5000 { 171 compatible = "arm,cci-400-ctrl-if"; 172 interface-type = "ace"; 173 reg = <0x5000 0x1000>; 174 }; 175 }; 176 177 clock: clock-controller@10010000 { 178 compatible = "samsung,exynos5420-clock", "syscon"; 179 reg = <0x10010000 0x30000>; 180 #clock-cells = <1>; 181 }; 182 183 clock_audss: audss-clock-controller@3810000 { 184 compatible = "samsung,exynos5420-audss-clock"; 185 reg = <0x03810000 0x0C>; 186 #clock-cells = <1>; 187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 190 power-domains = <&mau_pd>; 191 }; 192 193 mfc: codec@11000000 { 194 compatible = "samsung,mfc-v7"; 195 reg = <0x11000000 0x10000>; 196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clock CLK_MFC>; 198 clock-names = "mfc"; 199 power-domains = <&mfc_pd>; 200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 201 iommu-names = "left", "right"; 202 }; 203 204 mmc_0: mmc@12200000 { 205 compatible = "samsung,exynos5420-dw-mshc-smu"; 206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <0x12200000 0x2000>; 210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 211 clock-names = "biu", "ciu"; 212 fifo-depth = <0x40>; 213 status = "disabled"; 214 }; 215 216 mmc_1: mmc@12210000 { 217 compatible = "samsung,exynos5420-dw-mshc-smu"; 218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x12210000 0x2000>; 222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 223 clock-names = "biu", "ciu"; 224 fifo-depth = <0x40>; 225 status = "disabled"; 226 }; 227 228 mmc_2: mmc@12220000 { 229 compatible = "samsung,exynos5420-dw-mshc"; 230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0x12220000 0x1000>; 234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 235 clock-names = "biu", "ciu"; 236 fifo-depth = <0x40>; 237 status = "disabled"; 238 }; 239 240 dmc: memory-controller@10c20000 { 241 compatible = "samsung,exynos5422-dmc"; 242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; 243 interrupt-parent = <&combiner>; 244 interrupts = <16 0>, <16 1>; 245 interrupt-names = "drex_0", "drex_1"; 246 clocks = <&clock CLK_FOUT_SPLL>, 247 <&clock CLK_MOUT_SCLK_SPLL>, 248 <&clock CLK_FF_DOUT_SPLL2>, 249 <&clock CLK_FOUT_BPLL>, 250 <&clock CLK_MOUT_BPLL>, 251 <&clock CLK_SCLK_BPLL>, 252 <&clock CLK_MOUT_MX_MSPLL_CCORE>, 253 <&clock CLK_MOUT_MCLK_CDREX>; 254 clock-names = "fout_spll", 255 "mout_sclk_spll", 256 "ff_dout_spll2", 257 "fout_bpll", 258 "mout_bpll", 259 "sclk_bpll", 260 "mout_mx_mspll_ccore", 261 "mout_mclk_cdrex"; 262 samsung,syscon-clk = <&clock>; 263 status = "disabled"; 264 }; 265 266 nocp_mem0_0: nocp@10ca1000 { 267 compatible = "samsung,exynos5420-nocp"; 268 reg = <0x10CA1000 0x200>; 269 status = "disabled"; 270 }; 271 272 nocp_mem0_1: nocp@10ca1400 { 273 compatible = "samsung,exynos5420-nocp"; 274 reg = <0x10CA1400 0x200>; 275 status = "disabled"; 276 }; 277 278 nocp_mem1_0: nocp@10ca1800 { 279 compatible = "samsung,exynos5420-nocp"; 280 reg = <0x10CA1800 0x200>; 281 status = "disabled"; 282 }; 283 284 nocp_mem1_1: nocp@10ca1c00 { 285 compatible = "samsung,exynos5420-nocp"; 286 reg = <0x10CA1C00 0x200>; 287 status = "disabled"; 288 }; 289 290 nocp_g3d_0: nocp@11a51000 { 291 compatible = "samsung,exynos5420-nocp"; 292 reg = <0x11A51000 0x200>; 293 status = "disabled"; 294 }; 295 296 nocp_g3d_1: nocp@11a51400 { 297 compatible = "samsung,exynos5420-nocp"; 298 reg = <0x11A51400 0x200>; 299 status = "disabled"; 300 }; 301 302 ppmu_dmc0_0: ppmu@10d00000 { 303 compatible = "samsung,exynos-ppmu"; 304 reg = <0x10d00000 0x2000>; 305 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; 306 clock-names = "ppmu"; 307 events { 308 ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { 309 event-name = "ppmu-event3-dmc0_0"; 310 }; 311 }; 312 }; 313 314 ppmu_dmc0_1: ppmu@10d10000 { 315 compatible = "samsung,exynos-ppmu"; 316 reg = <0x10d10000 0x2000>; 317 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; 318 clock-names = "ppmu"; 319 events { 320 ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { 321 event-name = "ppmu-event3-dmc0_1"; 322 }; 323 }; 324 }; 325 326 ppmu_dmc1_0: ppmu@10d60000 { 327 compatible = "samsung,exynos-ppmu"; 328 reg = <0x10d60000 0x2000>; 329 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; 330 clock-names = "ppmu"; 331 events { 332 ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { 333 event-name = "ppmu-event3-dmc1_0"; 334 }; 335 }; 336 }; 337 338 ppmu_dmc1_1: ppmu@10d70000 { 339 compatible = "samsung,exynos-ppmu"; 340 reg = <0x10d70000 0x2000>; 341 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; 342 clock-names = "ppmu"; 343 events { 344 ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { 345 event-name = "ppmu-event3-dmc1_1"; 346 }; 347 }; 348 }; 349 350 gsc_pd: power-domain@10044000 { 351 compatible = "samsung,exynos4210-pd"; 352 reg = <0x10044000 0x20>; 353 #power-domain-cells = <0>; 354 label = "GSC"; 355 }; 356 357 isp_pd: power-domain@10044020 { 358 compatible = "samsung,exynos4210-pd"; 359 reg = <0x10044020 0x20>; 360 #power-domain-cells = <0>; 361 label = "ISP"; 362 }; 363 364 mfc_pd: power-domain@10044060 { 365 compatible = "samsung,exynos4210-pd"; 366 reg = <0x10044060 0x20>; 367 #power-domain-cells = <0>; 368 label = "MFC"; 369 }; 370 371 g3d_pd: power-domain@10044080 { 372 compatible = "samsung,exynos4210-pd"; 373 reg = <0x10044080 0x20>; 374 #power-domain-cells = <0>; 375 label = "G3D"; 376 }; 377 378 disp_pd: power-domain@100440c0 { 379 compatible = "samsung,exynos4210-pd"; 380 reg = <0x100440C0 0x20>; 381 #power-domain-cells = <0>; 382 label = "DISP"; 383 }; 384 385 mau_pd: power-domain@100440e0 { 386 compatible = "samsung,exynos4210-pd"; 387 reg = <0x100440E0 0x20>; 388 #power-domain-cells = <0>; 389 label = "MAU"; 390 }; 391 392 msc_pd: power-domain@10044120 { 393 compatible = "samsung,exynos4210-pd"; 394 reg = <0x10044120 0x20>; 395 #power-domain-cells = <0>; 396 label = "MSC"; 397 }; 398 399 pinctrl_0: pinctrl@13400000 { 400 compatible = "samsung,exynos5420-pinctrl"; 401 reg = <0x13400000 0x1000>; 402 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 403 404 wakeup-interrupt-controller { 405 compatible = "samsung,exynos4210-wakeup-eint"; 406 interrupt-parent = <&gic>; 407 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 408 }; 409 }; 410 411 pinctrl_1: pinctrl@13410000 { 412 compatible = "samsung,exynos5420-pinctrl"; 413 reg = <0x13410000 0x1000>; 414 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 415 }; 416 417 pinctrl_2: pinctrl@14000000 { 418 compatible = "samsung,exynos5420-pinctrl"; 419 reg = <0x14000000 0x1000>; 420 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 421 }; 422 423 pinctrl_3: pinctrl@14010000 { 424 compatible = "samsung,exynos5420-pinctrl"; 425 reg = <0x14010000 0x1000>; 426 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 429 pinctrl_4: pinctrl@3860000 { 430 compatible = "samsung,exynos5420-pinctrl"; 431 reg = <0x03860000 0x1000>; 432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 433 power-domains = <&mau_pd>; 434 }; 435 436 adma: adma@3880000 { 437 compatible = "arm,pl330", "arm,primecell"; 438 reg = <0x03880000 0x1000>; 439 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clock_audss EXYNOS_ADMA>; 441 clock-names = "apb_pclk"; 442 #dma-cells = <1>; 443 #dma-channels = <6>; 444 #dma-requests = <16>; 445 power-domains = <&mau_pd>; 446 }; 447 448 pdma0: pdma@121a0000 { 449 compatible = "arm,pl330", "arm,primecell"; 450 reg = <0x121A0000 0x1000>; 451 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clock CLK_PDMA0>; 453 clock-names = "apb_pclk"; 454 #dma-cells = <1>; 455 #dma-channels = <8>; 456 #dma-requests = <32>; 457 }; 458 459 pdma1: pdma@121b0000 { 460 compatible = "arm,pl330", "arm,primecell"; 461 reg = <0x121B0000 0x1000>; 462 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clock CLK_PDMA1>; 464 clock-names = "apb_pclk"; 465 #dma-cells = <1>; 466 #dma-channels = <8>; 467 #dma-requests = <32>; 468 }; 469 470 mdma0: mdma@10800000 { 471 compatible = "arm,pl330", "arm,primecell"; 472 reg = <0x10800000 0x1000>; 473 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clock CLK_MDMA0>; 475 clock-names = "apb_pclk"; 476 #dma-cells = <1>; 477 #dma-channels = <8>; 478 #dma-requests = <1>; 479 }; 480 481 mdma1: mdma@11c10000 { 482 compatible = "arm,pl330", "arm,primecell"; 483 reg = <0x11C10000 0x1000>; 484 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&clock CLK_MDMA1>; 486 clock-names = "apb_pclk"; 487 #dma-cells = <1>; 488 #dma-channels = <8>; 489 #dma-requests = <1>; 490 /* 491 * MDMA1 can support both secure and non-secure 492 * AXI transactions. When this is enabled in 493 * the kernel for boards that run in secure 494 * mode, we are getting imprecise external 495 * aborts causing the kernel to oops. 496 */ 497 status = "disabled"; 498 }; 499 500 i2s0: i2s@3830000 { 501 compatible = "samsung,exynos5420-i2s"; 502 reg = <0x03830000 0x100>; 503 dmas = <&adma 0>, 504 <&adma 2>, 505 <&adma 1>; 506 dma-names = "tx", "rx", "tx-sec"; 507 clocks = <&clock_audss EXYNOS_I2S_BUS>, 508 <&clock_audss EXYNOS_I2S_BUS>, 509 <&clock_audss EXYNOS_SCLK_I2S>; 510 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 511 #clock-cells = <1>; 512 clock-output-names = "i2s_cdclk0"; 513 #sound-dai-cells = <1>; 514 samsung,idma-addr = <0x03000000>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2s0_bus>; 517 power-domains = <&mau_pd>; 518 status = "disabled"; 519 }; 520 521 i2s1: i2s@12d60000 { 522 compatible = "samsung,exynos5420-i2s"; 523 reg = <0x12D60000 0x100>; 524 dmas = <&pdma1 12>, 525 <&pdma1 11>; 526 dma-names = "tx", "rx"; 527 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 528 clock-names = "iis", "i2s_opclk0"; 529 #clock-cells = <1>; 530 clock-output-names = "i2s_cdclk1"; 531 #sound-dai-cells = <1>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&i2s1_bus>; 534 status = "disabled"; 535 }; 536 537 i2s2: i2s@12d70000 { 538 compatible = "samsung,exynos5420-i2s"; 539 reg = <0x12D70000 0x100>; 540 dmas = <&pdma0 12>, 541 <&pdma0 11>; 542 dma-names = "tx", "rx"; 543 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 544 clock-names = "iis", "i2s_opclk0"; 545 #clock-cells = <1>; 546 clock-output-names = "i2s_cdclk2"; 547 #sound-dai-cells = <1>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2s2_bus>; 550 status = "disabled"; 551 }; 552 553 spi_0: spi@12d20000 { 554 compatible = "samsung,exynos4210-spi"; 555 reg = <0x12d20000 0x100>; 556 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 557 dmas = <&pdma0 5 558 &pdma0 4>; 559 dma-names = "tx", "rx"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&spi0_bus>; 564 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 565 clock-names = "spi", "spi_busclk0"; 566 status = "disabled"; 567 }; 568 569 spi_1: spi@12d30000 { 570 compatible = "samsung,exynos4210-spi"; 571 reg = <0x12d30000 0x100>; 572 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 573 dmas = <&pdma1 5 574 &pdma1 4>; 575 dma-names = "tx", "rx"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&spi1_bus>; 580 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 581 clock-names = "spi", "spi_busclk0"; 582 status = "disabled"; 583 }; 584 585 spi_2: spi@12d40000 { 586 compatible = "samsung,exynos4210-spi"; 587 reg = <0x12d40000 0x100>; 588 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 589 dmas = <&pdma0 7 590 &pdma0 6>; 591 dma-names = "tx", "rx"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&spi2_bus>; 596 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 597 clock-names = "spi", "spi_busclk0"; 598 status = "disabled"; 599 }; 600 601 dp_phy: dp-video-phy { 602 compatible = "samsung,exynos5420-dp-video-phy"; 603 samsung,pmu-syscon = <&pmu_system_controller>; 604 #phy-cells = <0>; 605 }; 606 607 mipi_phy: mipi-video-phy { 608 compatible = "samsung,s5pv210-mipi-video-phy"; 609 syscon = <&pmu_system_controller>; 610 #phy-cells = <1>; 611 }; 612 613 dsi@14500000 { 614 compatible = "samsung,exynos5410-mipi-dsi"; 615 reg = <0x14500000 0x10000>; 616 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 617 phys = <&mipi_phy 1>; 618 phy-names = "dsim"; 619 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 620 clock-names = "bus_clk", "pll_clk"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 hsi2c_8: i2c@12e00000 { 627 compatible = "samsung,exynos5250-hsi2c"; 628 reg = <0x12E00000 0x1000>; 629 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&i2c8_hs_bus>; 634 clocks = <&clock CLK_USI4>; 635 clock-names = "hsi2c"; 636 status = "disabled"; 637 }; 638 639 hsi2c_9: i2c@12e10000 { 640 compatible = "samsung,exynos5250-hsi2c"; 641 reg = <0x12E10000 0x1000>; 642 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&i2c9_hs_bus>; 647 clocks = <&clock CLK_USI5>; 648 clock-names = "hsi2c"; 649 status = "disabled"; 650 }; 651 652 hsi2c_10: i2c@12e20000 { 653 compatible = "samsung,exynos5250-hsi2c"; 654 reg = <0x12E20000 0x1000>; 655 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&i2c10_hs_bus>; 660 clocks = <&clock CLK_USI6>; 661 clock-names = "hsi2c"; 662 status = "disabled"; 663 }; 664 665 hdmi: hdmi@14530000 { 666 compatible = "samsung,exynos5420-hdmi"; 667 reg = <0x14530000 0x70000>; 668 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 670 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 671 <&clock CLK_MOUT_HDMI>; 672 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 673 "sclk_hdmiphy", "mout_hdmi"; 674 phy = <&hdmiphy>; 675 samsung,syscon-phandle = <&pmu_system_controller>; 676 status = "disabled"; 677 power-domains = <&disp_pd>; 678 #sound-dai-cells = <0>; 679 }; 680 681 hdmiphy: hdmiphy@145d0000 { 682 reg = <0x145D0000 0x20>; 683 }; 684 685 hdmicec: cec@101b0000 { 686 compatible = "samsung,s5p-cec"; 687 reg = <0x101B0000 0x200>; 688 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clock CLK_HDMI_CEC>; 690 clock-names = "hdmicec"; 691 samsung,syscon-phandle = <&pmu_system_controller>; 692 hdmi-phandle = <&hdmi>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&hdmi_cec>; 695 status = "disabled"; 696 }; 697 698 mixer: mixer@14450000 { 699 compatible = "samsung,exynos5420-mixer"; 700 reg = <0x14450000 0x10000>; 701 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 703 <&clock CLK_SCLK_HDMI>; 704 clock-names = "mixer", "hdmi", "sclk_hdmi"; 705 power-domains = <&disp_pd>; 706 iommus = <&sysmmu_tv>; 707 status = "disabled"; 708 }; 709 710 rotator: rotator@11c00000 { 711 compatible = "samsung,exynos5250-rotator"; 712 reg = <0x11C00000 0x64>; 713 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clock CLK_ROTATOR>; 715 clock-names = "rotator"; 716 iommus = <&sysmmu_rotator>; 717 }; 718 719 gsc_0: video-scaler@13e00000 { 720 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 721 reg = <0x13e00000 0x1000>; 722 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&clock CLK_GSCL0>; 724 clock-names = "gscl"; 725 power-domains = <&gsc_pd>; 726 iommus = <&sysmmu_gscl0>; 727 }; 728 729 gsc_1: video-scaler@13e10000 { 730 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 731 reg = <0x13e10000 0x1000>; 732 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&clock CLK_GSCL1>; 734 clock-names = "gscl"; 735 power-domains = <&gsc_pd>; 736 iommus = <&sysmmu_gscl1>; 737 }; 738 739 gpu: gpu@11800000 { 740 compatible = "samsung,exynos5420-mali", "arm,mali-t628"; 741 reg = <0x11800000 0x5000>; 742 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-names = "job", "mmu", "gpu"; 746 747 clocks = <&clock CLK_G3D>; 748 clock-names = "core"; 749 power-domains = <&g3d_pd>; 750 operating-points-v2 = <&gpu_opp_table>; 751 752 status = "disabled"; 753 #cooling-cells = <2>; 754 755 gpu_opp_table: opp-table { 756 compatible = "operating-points-v2"; 757 758 opp-177000000 { 759 opp-hz = /bits/ 64 <177000000>; 760 opp-microvolt = <812500>; 761 }; 762 opp-266000000 { 763 opp-hz = /bits/ 64 <266000000>; 764 opp-microvolt = <862500>; 765 }; 766 opp-350000000 { 767 opp-hz = /bits/ 64 <350000000>; 768 opp-microvolt = <912500>; 769 }; 770 opp-420000000 { 771 opp-hz = /bits/ 64 <420000000>; 772 opp-microvolt = <962500>; 773 }; 774 opp-480000000 { 775 opp-hz = /bits/ 64 <480000000>; 776 opp-microvolt = <1000000>; 777 }; 778 opp-543000000 { 779 opp-hz = /bits/ 64 <543000000>; 780 opp-microvolt = <1037500>; 781 }; 782 opp-600000000 { 783 opp-hz = /bits/ 64 <600000000>; 784 opp-microvolt = <1150000>; 785 }; 786 }; 787 }; 788 789 scaler_0: scaler@12800000 { 790 compatible = "samsung,exynos5420-scaler"; 791 reg = <0x12800000 0x1294>; 792 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&clock CLK_MSCL0>; 794 clock-names = "mscl"; 795 power-domains = <&msc_pd>; 796 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; 797 }; 798 799 scaler_1: scaler@12810000 { 800 compatible = "samsung,exynos5420-scaler"; 801 reg = <0x12810000 0x1294>; 802 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clock CLK_MSCL1>; 804 clock-names = "mscl"; 805 power-domains = <&msc_pd>; 806 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; 807 }; 808 809 scaler_2: scaler@12820000 { 810 compatible = "samsung,exynos5420-scaler"; 811 reg = <0x12820000 0x1294>; 812 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clock CLK_MSCL2>; 814 clock-names = "mscl"; 815 power-domains = <&msc_pd>; 816 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; 817 }; 818 819 jpeg_0: jpeg@11f50000 { 820 compatible = "samsung,exynos5420-jpeg"; 821 reg = <0x11F50000 0x1000>; 822 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 823 clock-names = "jpeg"; 824 clocks = <&clock CLK_JPEG>; 825 iommus = <&sysmmu_jpeg0>; 826 }; 827 828 jpeg_1: jpeg@11f60000 { 829 compatible = "samsung,exynos5420-jpeg"; 830 reg = <0x11F60000 0x1000>; 831 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 832 clock-names = "jpeg"; 833 clocks = <&clock CLK_JPEG2>; 834 iommus = <&sysmmu_jpeg1>; 835 }; 836 837 pmu_system_controller: system-controller@10040000 { 838 compatible = "samsung,exynos5420-pmu", "syscon"; 839 reg = <0x10040000 0x5000>; 840 clock-names = "clkout16"; 841 clocks = <&clock CLK_FIN_PLL>; 842 #clock-cells = <1>; 843 interrupt-controller; 844 #interrupt-cells = <3>; 845 interrupt-parent = <&gic>; 846 }; 847 848 tmu_cpu0: tmu@10060000 { 849 compatible = "samsung,exynos5420-tmu"; 850 reg = <0x10060000 0x100>; 851 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clock CLK_TMU>; 853 clock-names = "tmu_apbif"; 854 #thermal-sensor-cells = <0>; 855 }; 856 857 tmu_cpu1: tmu@10064000 { 858 compatible = "samsung,exynos5420-tmu"; 859 reg = <0x10064000 0x100>; 860 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clock CLK_TMU>; 862 clock-names = "tmu_apbif"; 863 #thermal-sensor-cells = <0>; 864 }; 865 866 tmu_cpu2: tmu@10068000 { 867 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 868 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 869 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 871 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 872 #thermal-sensor-cells = <0>; 873 }; 874 875 tmu_cpu3: tmu@1006c000 { 876 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 877 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 878 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 880 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 881 #thermal-sensor-cells = <0>; 882 }; 883 884 tmu_gpu: tmu@100a0000 { 885 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 886 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 887 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 889 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 890 #thermal-sensor-cells = <0>; 891 }; 892 893 sysmmu_g2dr: sysmmu@10a60000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x10A60000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <24 5>; 898 clock-names = "sysmmu", "master"; 899 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 900 #iommu-cells = <0>; 901 }; 902 903 sysmmu_g2dw: sysmmu@10a70000 { 904 compatible = "samsung,exynos-sysmmu"; 905 reg = <0x10A70000 0x1000>; 906 interrupt-parent = <&combiner>; 907 interrupts = <22 2>; 908 clock-names = "sysmmu", "master"; 909 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 910 #iommu-cells = <0>; 911 }; 912 913 sysmmu_tv: sysmmu@14650000 { 914 compatible = "samsung,exynos-sysmmu"; 915 reg = <0x14650000 0x1000>; 916 interrupt-parent = <&combiner>; 917 interrupts = <7 4>; 918 clock-names = "sysmmu", "master"; 919 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; 920 power-domains = <&disp_pd>; 921 #iommu-cells = <0>; 922 }; 923 924 sysmmu_gscl0: sysmmu@13e80000 { 925 compatible = "samsung,exynos-sysmmu"; 926 reg = <0x13E80000 0x1000>; 927 interrupt-parent = <&combiner>; 928 interrupts = <2 0>; 929 clock-names = "sysmmu", "master"; 930 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 931 power-domains = <&gsc_pd>; 932 #iommu-cells = <0>; 933 }; 934 935 sysmmu_gscl1: sysmmu@13e90000 { 936 compatible = "samsung,exynos-sysmmu"; 937 reg = <0x13E90000 0x1000>; 938 interrupt-parent = <&combiner>; 939 interrupts = <2 2>; 940 clock-names = "sysmmu", "master"; 941 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 942 power-domains = <&gsc_pd>; 943 #iommu-cells = <0>; 944 }; 945 946 sysmmu_scaler0r: sysmmu@12880000 { 947 compatible = "samsung,exynos-sysmmu"; 948 reg = <0x12880000 0x1000>; 949 interrupt-parent = <&combiner>; 950 interrupts = <22 4>; 951 clock-names = "sysmmu", "master"; 952 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 953 power-domains = <&msc_pd>; 954 #iommu-cells = <0>; 955 }; 956 957 sysmmu_scaler1r: sysmmu@12890000 { 958 compatible = "samsung,exynos-sysmmu"; 959 reg = <0x12890000 0x1000>; 960 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 961 clock-names = "sysmmu", "master"; 962 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 963 power-domains = <&msc_pd>; 964 #iommu-cells = <0>; 965 }; 966 967 sysmmu_scaler2r: sysmmu@128a0000 { 968 compatible = "samsung,exynos-sysmmu"; 969 reg = <0x128A0000 0x1000>; 970 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 971 clock-names = "sysmmu", "master"; 972 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 973 power-domains = <&msc_pd>; 974 #iommu-cells = <0>; 975 }; 976 977 sysmmu_scaler0w: sysmmu@128c0000 { 978 compatible = "samsung,exynos-sysmmu"; 979 reg = <0x128C0000 0x1000>; 980 interrupt-parent = <&combiner>; 981 interrupts = <27 2>; 982 clock-names = "sysmmu", "master"; 983 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 984 power-domains = <&msc_pd>; 985 #iommu-cells = <0>; 986 }; 987 988 sysmmu_scaler1w: sysmmu@128d0000 { 989 compatible = "samsung,exynos-sysmmu"; 990 reg = <0x128D0000 0x1000>; 991 interrupt-parent = <&combiner>; 992 interrupts = <22 6>; 993 clock-names = "sysmmu", "master"; 994 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 995 power-domains = <&msc_pd>; 996 #iommu-cells = <0>; 997 }; 998 999 sysmmu_scaler2w: sysmmu@128e0000 { 1000 compatible = "samsung,exynos-sysmmu"; 1001 reg = <0x128E0000 0x1000>; 1002 interrupt-parent = <&combiner>; 1003 interrupts = <19 6>; 1004 clock-names = "sysmmu", "master"; 1005 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 1006 power-domains = <&msc_pd>; 1007 #iommu-cells = <0>; 1008 }; 1009 1010 sysmmu_rotator: sysmmu@11d40000 { 1011 compatible = "samsung,exynos-sysmmu"; 1012 reg = <0x11D40000 0x1000>; 1013 interrupt-parent = <&combiner>; 1014 interrupts = <4 0>; 1015 clock-names = "sysmmu", "master"; 1016 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 1017 #iommu-cells = <0>; 1018 }; 1019 1020 sysmmu_jpeg0: sysmmu@11f10000 { 1021 compatible = "samsung,exynos-sysmmu"; 1022 reg = <0x11F10000 0x1000>; 1023 interrupt-parent = <&combiner>; 1024 interrupts = <4 2>; 1025 clock-names = "sysmmu", "master"; 1026 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 1027 #iommu-cells = <0>; 1028 }; 1029 1030 sysmmu_jpeg1: sysmmu@11f20000 { 1031 compatible = "samsung,exynos-sysmmu"; 1032 reg = <0x11F20000 0x1000>; 1033 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1034 clock-names = "sysmmu", "master"; 1035 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 1036 #iommu-cells = <0>; 1037 }; 1038 1039 sysmmu_mfc_l: sysmmu@11200000 { 1040 compatible = "samsung,exynos-sysmmu"; 1041 reg = <0x11200000 0x1000>; 1042 interrupt-parent = <&combiner>; 1043 interrupts = <6 2>; 1044 clock-names = "sysmmu", "master"; 1045 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 1046 power-domains = <&mfc_pd>; 1047 #iommu-cells = <0>; 1048 }; 1049 1050 sysmmu_mfc_r: sysmmu@11210000 { 1051 compatible = "samsung,exynos-sysmmu"; 1052 reg = <0x11210000 0x1000>; 1053 interrupt-parent = <&combiner>; 1054 interrupts = <8 5>; 1055 clock-names = "sysmmu", "master"; 1056 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 1057 power-domains = <&mfc_pd>; 1058 #iommu-cells = <0>; 1059 }; 1060 1061 sysmmu_fimd1_0: sysmmu@14640000 { 1062 compatible = "samsung,exynos-sysmmu"; 1063 reg = <0x14640000 0x1000>; 1064 interrupt-parent = <&combiner>; 1065 interrupts = <3 2>; 1066 clock-names = "sysmmu", "master"; 1067 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; 1068 power-domains = <&disp_pd>; 1069 #iommu-cells = <0>; 1070 }; 1071 1072 sysmmu_fimd1_1: sysmmu@14680000 { 1073 compatible = "samsung,exynos-sysmmu"; 1074 reg = <0x14680000 0x1000>; 1075 interrupt-parent = <&combiner>; 1076 interrupts = <3 0>; 1077 clock-names = "sysmmu", "master"; 1078 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; 1079 power-domains = <&disp_pd>; 1080 #iommu-cells = <0>; 1081 }; 1082 1083 bus_wcore: bus_wcore { 1084 compatible = "samsung,exynos-bus"; 1085 clocks = <&clock CLK_DOUT_ACLK400_WCORE>; 1086 clock-names = "bus"; 1087 status = "disabled"; 1088 }; 1089 1090 bus_noc: bus_noc { 1091 compatible = "samsung,exynos-bus"; 1092 clocks = <&clock CLK_DOUT_ACLK100_NOC>; 1093 clock-names = "bus"; 1094 status = "disabled"; 1095 }; 1096 1097 bus_fsys_apb: bus_fsys_apb { 1098 compatible = "samsung,exynos-bus"; 1099 clocks = <&clock CLK_DOUT_PCLK200_FSYS>; 1100 clock-names = "bus"; 1101 status = "disabled"; 1102 }; 1103 1104 bus_fsys: bus_fsys { 1105 compatible = "samsung,exynos-bus"; 1106 clocks = <&clock CLK_DOUT_ACLK200_FSYS>; 1107 clock-names = "bus"; 1108 status = "disabled"; 1109 }; 1110 1111 bus_fsys2: bus_fsys2 { 1112 compatible = "samsung,exynos-bus"; 1113 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; 1114 clock-names = "bus"; 1115 status = "disabled"; 1116 }; 1117 1118 bus_mfc: bus_mfc { 1119 compatible = "samsung,exynos-bus"; 1120 clocks = <&clock CLK_DOUT_ACLK333>; 1121 clock-names = "bus"; 1122 status = "disabled"; 1123 }; 1124 1125 bus_gen: bus_gen { 1126 compatible = "samsung,exynos-bus"; 1127 clocks = <&clock CLK_DOUT_ACLK266>; 1128 clock-names = "bus"; 1129 status = "disabled"; 1130 }; 1131 1132 bus_peri: bus_peri { 1133 compatible = "samsung,exynos-bus"; 1134 clocks = <&clock CLK_DOUT_ACLK66>; 1135 clock-names = "bus"; 1136 status = "disabled"; 1137 }; 1138 1139 bus_g2d: bus_g2d { 1140 compatible = "samsung,exynos-bus"; 1141 clocks = <&clock CLK_DOUT_ACLK333_G2D>; 1142 clock-names = "bus"; 1143 status = "disabled"; 1144 }; 1145 1146 bus_g2d_acp: bus_g2d_acp { 1147 compatible = "samsung,exynos-bus"; 1148 clocks = <&clock CLK_DOUT_ACLK266_G2D>; 1149 clock-names = "bus"; 1150 status = "disabled"; 1151 }; 1152 1153 bus_jpeg: bus_jpeg { 1154 compatible = "samsung,exynos-bus"; 1155 clocks = <&clock CLK_DOUT_ACLK300_JPEG>; 1156 clock-names = "bus"; 1157 status = "disabled"; 1158 }; 1159 1160 bus_jpeg_apb: bus_jpeg_apb { 1161 compatible = "samsung,exynos-bus"; 1162 clocks = <&clock CLK_DOUT_ACLK166>; 1163 clock-names = "bus"; 1164 status = "disabled"; 1165 }; 1166 1167 bus_disp1_fimd: bus_disp1_fimd { 1168 compatible = "samsung,exynos-bus"; 1169 clocks = <&clock CLK_DOUT_ACLK300_DISP1>; 1170 clock-names = "bus"; 1171 status = "disabled"; 1172 }; 1173 1174 bus_disp1: bus_disp1 { 1175 compatible = "samsung,exynos-bus"; 1176 clocks = <&clock CLK_DOUT_ACLK400_DISP1>; 1177 clock-names = "bus"; 1178 status = "disabled"; 1179 }; 1180 1181 bus_gscl_scaler: bus_gscl_scaler { 1182 compatible = "samsung,exynos-bus"; 1183 clocks = <&clock CLK_DOUT_ACLK300_GSCL>; 1184 clock-names = "bus"; 1185 status = "disabled"; 1186 }; 1187 1188 bus_mscl: bus_mscl { 1189 compatible = "samsung,exynos-bus"; 1190 clocks = <&clock CLK_DOUT_ACLK400_MSCL>; 1191 clock-names = "bus"; 1192 status = "disabled"; 1193 }; 1194 }; 1195 1196 thermal-zones { 1197 cpu0_thermal: cpu0-thermal { 1198 thermal-sensors = <&tmu_cpu0>; 1199 #include "exynos5420-trip-points.dtsi" 1200 }; 1201 cpu1_thermal: cpu1-thermal { 1202 thermal-sensors = <&tmu_cpu1>; 1203 #include "exynos5420-trip-points.dtsi" 1204 }; 1205 cpu2_thermal: cpu2-thermal { 1206 thermal-sensors = <&tmu_cpu2>; 1207 #include "exynos5420-trip-points.dtsi" 1208 }; 1209 cpu3_thermal: cpu3-thermal { 1210 thermal-sensors = <&tmu_cpu3>; 1211 #include "exynos5420-trip-points.dtsi" 1212 }; 1213 gpu_thermal: gpu-thermal { 1214 thermal-sensors = <&tmu_gpu>; 1215 #include "exynos5420-trip-points.dtsi" 1216 }; 1217 }; 1218}; 1219 1220&adc { 1221 clocks = <&clock CLK_TSADC>; 1222 clock-names = "adc"; 1223 samsung,syscon-phandle = <&pmu_system_controller>; 1224}; 1225 1226&dp { 1227 clocks = <&clock CLK_DP1>; 1228 clock-names = "dp"; 1229 phys = <&dp_phy>; 1230 phy-names = "dp"; 1231 power-domains = <&disp_pd>; 1232}; 1233 1234&fimd { 1235 compatible = "samsung,exynos5420-fimd"; 1236 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1237 clock-names = "sclk_fimd", "fimd"; 1238 power-domains = <&disp_pd>; 1239 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; 1240 iommu-names = "m0", "m1"; 1241}; 1242 1243&g2d { 1244 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; 1245 clocks = <&clock CLK_G2D>; 1246 clock-names = "fimg2d"; 1247 status = "okay"; 1248}; 1249 1250&i2c_0 { 1251 clocks = <&clock CLK_I2C0>; 1252 clock-names = "i2c"; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&i2c0_bus>; 1255}; 1256 1257&i2c_1 { 1258 clocks = <&clock CLK_I2C1>; 1259 clock-names = "i2c"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&i2c1_bus>; 1262}; 1263 1264&i2c_2 { 1265 clocks = <&clock CLK_I2C2>; 1266 clock-names = "i2c"; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&i2c2_bus>; 1269}; 1270 1271&i2c_3 { 1272 clocks = <&clock CLK_I2C3>; 1273 clock-names = "i2c"; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&i2c3_bus>; 1276}; 1277 1278&hsi2c_4 { 1279 clocks = <&clock CLK_USI0>; 1280 clock-names = "hsi2c"; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&i2c4_hs_bus>; 1283}; 1284 1285&hsi2c_5 { 1286 clocks = <&clock CLK_USI1>; 1287 clock-names = "hsi2c"; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&i2c5_hs_bus>; 1290}; 1291 1292&hsi2c_6 { 1293 clocks = <&clock CLK_USI2>; 1294 clock-names = "hsi2c"; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&i2c6_hs_bus>; 1297}; 1298 1299&hsi2c_7 { 1300 clocks = <&clock CLK_USI3>; 1301 clock-names = "hsi2c"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&i2c7_hs_bus>; 1304}; 1305 1306&mct { 1307 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 1308 clock-names = "fin_pll", "mct"; 1309}; 1310 1311&prng { 1312 clocks = <&clock CLK_SSS>; 1313 clock-names = "secss"; 1314}; 1315 1316&pwm { 1317 clocks = <&clock CLK_PWM>; 1318 clock-names = "timers"; 1319}; 1320 1321&rtc { 1322 clocks = <&clock CLK_RTC>; 1323 clock-names = "rtc"; 1324 interrupt-parent = <&pmu_system_controller>; 1325 status = "disabled"; 1326}; 1327 1328&serial_0 { 1329 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1330 clock-names = "uart", "clk_uart_baud0"; 1331 dmas = <&pdma0 13>, <&pdma0 14>; 1332 dma-names = "rx", "tx"; 1333}; 1334 1335&serial_1 { 1336 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1337 clock-names = "uart", "clk_uart_baud0"; 1338 dmas = <&pdma1 15>, <&pdma1 16>; 1339 dma-names = "rx", "tx"; 1340}; 1341 1342&serial_2 { 1343 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1344 clock-names = "uart", "clk_uart_baud0"; 1345 dmas = <&pdma0 15>, <&pdma0 16>; 1346 dma-names = "rx", "tx"; 1347}; 1348 1349&serial_3 { 1350 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1351 clock-names = "uart", "clk_uart_baud0"; 1352 dmas = <&pdma1 17>, <&pdma1 18>; 1353 dma-names = "rx", "tx"; 1354}; 1355 1356&sss { 1357 clocks = <&clock CLK_SSS>; 1358 clock-names = "secss"; 1359}; 1360 1361&trng { 1362 clocks = <&clock CLK_SSS>; 1363 clock-names = "secss"; 1364}; 1365 1366&usbdrd3_0 { 1367 clocks = <&clock CLK_USBD300>; 1368 clock-names = "usbdrd30"; 1369}; 1370 1371&usbdrd_phy0 { 1372 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 1373 clock-names = "phy", "ref"; 1374 samsung,pmu-syscon = <&pmu_system_controller>; 1375}; 1376 1377&usbdrd3_1 { 1378 clocks = <&clock CLK_USBD301>; 1379 clock-names = "usbdrd30"; 1380}; 1381 1382&usbdrd_dwc3_1 { 1383 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1384}; 1385 1386&usbdrd_phy1 { 1387 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 1388 clock-names = "phy", "ref"; 1389 samsung,pmu-syscon = <&pmu_system_controller>; 1390}; 1391 1392&usbhost1 { 1393 clocks = <&clock CLK_USBH20>; 1394 clock-names = "usbhost"; 1395}; 1396 1397&usbhost2 { 1398 clocks = <&clock CLK_USBH20>; 1399 clock-names = "usbhost"; 1400}; 1401 1402&usb2_phy { 1403 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 1404 clock-names = "phy", "ref"; 1405 samsung,sysreg-phandle = <&sysreg_system_controller>; 1406 samsung,pmureg-phandle = <&pmu_system_controller>; 1407}; 1408 1409&watchdog { 1410 clocks = <&clock CLK_WDT>; 1411 clock-names = "watchdog"; 1412 samsung,syscon-phandle = <&pmu_system_controller>; 1413}; 1414 1415#include "exynos5420-pinctrl.dtsi" 1416#include "exynos-syscon-restart.dtsi" 1417