1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef __ICP_QAT_HAL_H 4 #define __ICP_QAT_HAL_H 5 #include "icp_qat_fw_loader_handle.h" 6 7 enum hal_global_csr { 8 MISC_CONTROL = 0x04, 9 ICP_RESET = 0x0c, 10 ICP_GLOBAL_CLK_ENABLE = 0x50 11 }; 12 13 enum hal_ae_csr { 14 USTORE_ADDRESS = 0x000, 15 USTORE_DATA_LOWER = 0x004, 16 USTORE_DATA_UPPER = 0x008, 17 ALU_OUT = 0x010, 18 CTX_ARB_CNTL = 0x014, 19 CTX_ENABLES = 0x018, 20 CC_ENABLE = 0x01c, 21 CSR_CTX_POINTER = 0x020, 22 CTX_STS_INDIRECT = 0x040, 23 ACTIVE_CTX_STATUS = 0x044, 24 CTX_SIG_EVENTS_INDIRECT = 0x048, 25 CTX_SIG_EVENTS_ACTIVE = 0x04c, 26 CTX_WAKEUP_EVENTS_INDIRECT = 0x050, 27 LM_ADDR_0_INDIRECT = 0x060, 28 LM_ADDR_1_INDIRECT = 0x068, 29 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, 30 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, 31 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, 32 TIMESTAMP_LOW = 0x0c0, 33 TIMESTAMP_HIGH = 0x0c4, 34 PROFILE_COUNT = 0x144, 35 SIGNATURE_ENABLE = 0x150, 36 AE_MISC_CONTROL = 0x160, 37 LOCAL_CSR_STATUS = 0x180, 38 }; 39 40 enum fcu_csr { 41 FCU_CONTROL = 0x8c0, 42 FCU_STATUS = 0x8c4, 43 FCU_STATUS1 = 0x8c8, 44 FCU_DRAM_ADDR_LO = 0x8cc, 45 FCU_DRAM_ADDR_HI = 0x8d0, 46 FCU_RAMBASE_ADDR_HI = 0x8d4, 47 FCU_RAMBASE_ADDR_LO = 0x8d8 48 }; 49 50 enum fcu_cmd { 51 FCU_CTRL_CMD_NOOP = 0, 52 FCU_CTRL_CMD_AUTH = 1, 53 FCU_CTRL_CMD_LOAD = 2, 54 FCU_CTRL_CMD_START = 3 55 }; 56 57 enum fcu_sts { 58 FCU_STS_NO_STS = 0, 59 FCU_STS_VERI_DONE = 1, 60 FCU_STS_LOAD_DONE = 2, 61 FCU_STS_VERI_FAIL = 3, 62 FCU_STS_LOAD_FAIL = 4, 63 FCU_STS_BUSY = 5 64 }; 65 #define UA_ECS (0x1 << 31) 66 #define ACS_ABO_BITPOS 31 67 #define ACS_ACNO 0x7 68 #define CE_ENABLE_BITPOS 0x8 69 #define CE_LMADDR_0_GLOBAL_BITPOS 16 70 #define CE_LMADDR_1_GLOBAL_BITPOS 17 71 #define CE_NN_MODE_BITPOS 20 72 #define CE_REG_PAR_ERR_BITPOS 25 73 #define CE_BREAKPOINT_BITPOS 27 74 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 75 #define CE_INUSE_CONTEXTS_BITPOS 31 76 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) 77 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) 78 #define XCWE_VOLUNTARY (0x1) 79 #define LCS_STATUS (0x1) 80 #define MMC_SHARE_CS_BITPOS 2 81 #define GLOBAL_CSR 0xA00 82 #define FCU_CTRL_AE_POS 0x8 83 #define FCU_AUTH_STS_MASK 0x7 84 #define FCU_STS_DONE_POS 0x9 85 #define FCU_STS_AUTHFWLD_POS 0X8 86 #define FCU_LOADED_AE_POS 0x16 87 #define FW_AUTH_WAIT_PERIOD 10 88 #define FW_AUTH_MAX_RETRY 300 89 90 #define SET_CAP_CSR(handle, csr, val) \ 91 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val) 92 #define GET_CAP_CSR(handle, csr) \ 93 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr) 94 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) 95 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr) 96 #define AE_CSR(handle, ae) \ 97 ((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \ 98 ((ae & handle->hal_handle->ae_mask) << 12)) 99 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr)) 100 #define SET_AE_CSR(handle, ae, csr, val) \ 101 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) 102 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) 103 #define AE_XFER(handle, ae) \ 104 ((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \ 105 ((ae & handle->hal_handle->ae_mask) << 12)) 106 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ 107 ((reg & 0xff) << 2)) 108 #define SET_AE_XFER(handle, ae, reg, val) \ 109 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) 110 #define SRAM_WRITE(handle, addr, val) \ 111 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val) 112 #endif 113