1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * Copyright (C) 2018 Renesas Electronics Corp. 7 * 8 */ 9 10 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 13 enum rcar_gen3_clk_types { 14 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 15 CLK_TYPE_GEN3_PLL0, 16 CLK_TYPE_GEN3_PLL1, 17 CLK_TYPE_GEN3_PLL2, 18 CLK_TYPE_GEN3_PLL3, 19 CLK_TYPE_GEN3_PLL4, 20 CLK_TYPE_GEN3_SD, 21 CLK_TYPE_GEN3_R, 22 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 23 CLK_TYPE_GEN3_Z, 24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 26 CLK_TYPE_GEN3_RPCSRC, 27 CLK_TYPE_GEN3_RPC, 28 CLK_TYPE_GEN3_RPCD2, 29 30 /* SoC specific definitions start here */ 31 CLK_TYPE_GEN3_SOC_BASE, 32 }; 33 34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 36 37 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 39 (_parent0) << 16 | (_parent1), \ 40 .div = (_div0) << 16 | (_div1), .offset = _md) 41 42 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 43 _div_clean) \ 44 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 45 _parent_clean, _div_clean) 46 47 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 48 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 49 50 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 51 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 52 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 53 54 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ 55 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 56 57 struct rcar_gen3_cpg_pll_config { 58 u8 extal_div; 59 u8 pll1_mult; 60 u8 pll1_div; 61 u8 pll3_mult; 62 u8 pll3_div; 63 u8 osc_prediv; 64 }; 65 66 #define CPG_RPCCKCR 0x238 67 #define CPG_RCKCR 0x240 68 69 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 70 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 71 struct clk **clks, void __iomem *base, 72 struct raw_notifier_head *notifiers); 73 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 74 unsigned int clk_extalr, u32 mode); 75 76 #endif 77