1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 mmc0 = &sdio0; 33 mmc1 = &sdmmc; 34 mmc2 = &sdhci; 35 serial0 = &uart0; 36 serial1 = &uart1; 37 serial2 = &uart2; 38 serial3 = &uart3; 39 serial4 = &uart4; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu_l0>; 50 }; 51 core1 { 52 cpu = <&cpu_l1>; 53 }; 54 core2 { 55 cpu = <&cpu_l2>; 56 }; 57 core3 { 58 cpu = <&cpu_l3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu_b0>; 65 }; 66 core1 { 67 cpu = <&cpu_b1>; 68 }; 69 }; 70 }; 71 72 cpu_l0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <485>; 78 clocks = <&cru ARMCLKL>; 79 #cooling-cells = <2>; /* min followed by max */ 80 dynamic-power-coefficient = <100>; 81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 82 }; 83 84 cpu_l1: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x1>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <485>; 90 clocks = <&cru ARMCLKL>; 91 #cooling-cells = <2>; /* min followed by max */ 92 dynamic-power-coefficient = <100>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 94 }; 95 96 cpu_l2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x2>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <485>; 102 clocks = <&cru ARMCLKL>; 103 #cooling-cells = <2>; /* min followed by max */ 104 dynamic-power-coefficient = <100>; 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 106 }; 107 108 cpu_l3: cpu@3 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x3>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&cru ARMCLKL>; 115 #cooling-cells = <2>; /* min followed by max */ 116 dynamic-power-coefficient = <100>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 }; 119 120 cpu_b0: cpu@100 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a72"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <1024>; 126 clocks = <&cru ARMCLKB>; 127 #cooling-cells = <2>; /* min followed by max */ 128 dynamic-power-coefficient = <436>; 129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 130 }; 131 132 cpu_b1: cpu@101 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a72"; 135 reg = <0x0 0x101>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 clocks = <&cru ARMCLKB>; 139 #cooling-cells = <2>; /* min followed by max */ 140 dynamic-power-coefficient = <436>; 141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 142 }; 143 144 idle-states { 145 entry-method = "psci"; 146 147 CPU_SLEEP: cpu-sleep { 148 compatible = "arm,idle-state"; 149 local-timer-stop; 150 arm,psci-suspend-param = <0x0010000>; 151 entry-latency-us = <120>; 152 exit-latency-us = <250>; 153 min-residency-us = <900>; 154 }; 155 156 CLUSTER_SLEEP: cluster-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x1010000>; 160 entry-latency-us = <400>; 161 exit-latency-us = <500>; 162 min-residency-us = <2000>; 163 }; 164 }; 165 }; 166 167 display-subsystem { 168 compatible = "rockchip,display-subsystem"; 169 ports = <&vopl_out>, <&vopb_out>; 170 }; 171 172 pmu_a53 { 173 compatible = "arm,cortex-a53-pmu"; 174 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 175 }; 176 177 pmu_a72 { 178 compatible = "arm,cortex-a72-pmu"; 179 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 180 }; 181 182 psci { 183 compatible = "arm,psci-1.0"; 184 method = "smc"; 185 }; 186 187 timer { 188 compatible = "arm,armv8-timer"; 189 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 190 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 191 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 192 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 193 arm,no-tick-in-suspend; 194 }; 195 196 xin24m: xin24m { 197 compatible = "fixed-clock"; 198 clock-frequency = <24000000>; 199 clock-output-names = "xin24m"; 200 #clock-cells = <0>; 201 }; 202 203 amba: bus { 204 compatible = "simple-bus"; 205 #address-cells = <2>; 206 #size-cells = <2>; 207 ranges; 208 209 dmac_bus: dma-controller@ff6d0000 { 210 compatible = "arm,pl330", "arm,primecell"; 211 reg = <0x0 0xff6d0000 0x0 0x4000>; 212 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 214 #dma-cells = <1>; 215 arm,pl330-periph-burst; 216 clocks = <&cru ACLK_DMAC0_PERILP>; 217 clock-names = "apb_pclk"; 218 }; 219 220 dmac_peri: dma-controller@ff6e0000 { 221 compatible = "arm,pl330", "arm,primecell"; 222 reg = <0x0 0xff6e0000 0x0 0x4000>; 223 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 224 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 225 #dma-cells = <1>; 226 arm,pl330-periph-burst; 227 clocks = <&cru ACLK_DMAC1_PERILP>; 228 clock-names = "apb_pclk"; 229 }; 230 }; 231 232 pcie0: pcie@f8000000 { 233 compatible = "rockchip,rk3399-pcie"; 234 reg = <0x0 0xf8000000 0x0 0x2000000>, 235 <0x0 0xfd000000 0x0 0x1000000>; 236 reg-names = "axi-base", "apb-base"; 237 device_type = "pci"; 238 #address-cells = <3>; 239 #size-cells = <2>; 240 #interrupt-cells = <1>; 241 aspm-no-l0s; 242 bus-range = <0x0 0x1f>; 243 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 244 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 245 clock-names = "aclk", "aclk-perf", 246 "hclk", "pm"; 247 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 248 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 249 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 250 interrupt-names = "sys", "legacy", "client"; 251 interrupt-map-mask = <0 0 0 7>; 252 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 253 <0 0 0 2 &pcie0_intc 1>, 254 <0 0 0 3 &pcie0_intc 2>, 255 <0 0 0 4 &pcie0_intc 3>; 256 max-link-speed = <1>; 257 msi-map = <0x0 &its 0x0 0x1000>; 258 phys = <&pcie_phy 0>, <&pcie_phy 1>, 259 <&pcie_phy 2>, <&pcie_phy 3>; 260 phy-names = "pcie-phy-0", "pcie-phy-1", 261 "pcie-phy-2", "pcie-phy-3"; 262 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 263 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 264 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 265 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 266 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 267 <&cru SRST_A_PCIE>; 268 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 269 "pm", "pclk", "aclk"; 270 status = "disabled"; 271 272 pcie0_intc: interrupt-controller { 273 interrupt-controller; 274 #address-cells = <0>; 275 #interrupt-cells = <1>; 276 }; 277 }; 278 279 gmac: ethernet@fe300000 { 280 compatible = "rockchip,rk3399-gmac"; 281 reg = <0x0 0xfe300000 0x0 0x10000>; 282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 283 interrupt-names = "macirq"; 284 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 285 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 286 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 287 <&cru PCLK_GMAC>; 288 clock-names = "stmmaceth", "mac_clk_rx", 289 "mac_clk_tx", "clk_mac_ref", 290 "clk_mac_refout", "aclk_mac", 291 "pclk_mac"; 292 power-domains = <&power RK3399_PD_GMAC>; 293 resets = <&cru SRST_A_GMAC>; 294 reset-names = "stmmaceth"; 295 rockchip,grf = <&grf>; 296 snps,txpbl = <0x4>; 297 status = "disabled"; 298 }; 299 300 sdio0: mmc@fe310000 { 301 compatible = "rockchip,rk3399-dw-mshc", 302 "rockchip,rk3288-dw-mshc"; 303 reg = <0x0 0xfe310000 0x0 0x4000>; 304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 305 max-frequency = <150000000>; 306 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 307 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 309 fifo-depth = <0x100>; 310 power-domains = <&power RK3399_PD_SDIOAUDIO>; 311 resets = <&cru SRST_SDIO0>; 312 reset-names = "reset"; 313 status = "disabled"; 314 }; 315 316 sdmmc: mmc@fe320000 { 317 compatible = "rockchip,rk3399-dw-mshc", 318 "rockchip,rk3288-dw-mshc"; 319 reg = <0x0 0xfe320000 0x0 0x4000>; 320 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 321 max-frequency = <150000000>; 322 assigned-clocks = <&cru HCLK_SD>; 323 assigned-clock-rates = <200000000>; 324 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 325 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 327 fifo-depth = <0x100>; 328 power-domains = <&power RK3399_PD_SD>; 329 resets = <&cru SRST_SDMMC>; 330 reset-names = "reset"; 331 status = "disabled"; 332 }; 333 334 sdhci: sdhci@fe330000 { 335 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 336 reg = <0x0 0xfe330000 0x0 0x10000>; 337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 338 arasan,soc-ctl-syscon = <&grf>; 339 assigned-clocks = <&cru SCLK_EMMC>; 340 assigned-clock-rates = <200000000>; 341 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 342 clock-names = "clk_xin", "clk_ahb"; 343 clock-output-names = "emmc_cardclock"; 344 #clock-cells = <0>; 345 phys = <&emmc_phy>; 346 phy-names = "phy_arasan"; 347 power-domains = <&power RK3399_PD_EMMC>; 348 disable-cqe-dcmd; 349 status = "disabled"; 350 }; 351 352 usb_host0_ehci: usb@fe380000 { 353 compatible = "generic-ehci"; 354 reg = <0x0 0xfe380000 0x0 0x20000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 357 <&u2phy0>; 358 phys = <&u2phy0_host>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 usb_host0_ohci: usb@fe3a0000 { 364 compatible = "generic-ohci"; 365 reg = <0x0 0xfe3a0000 0x0 0x20000>; 366 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 367 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 368 <&u2phy0>; 369 phys = <&u2phy0_host>; 370 phy-names = "usb"; 371 status = "disabled"; 372 }; 373 374 usb_host1_ehci: usb@fe3c0000 { 375 compatible = "generic-ehci"; 376 reg = <0x0 0xfe3c0000 0x0 0x20000>; 377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 379 <&u2phy1>; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 usb_host1_ohci: usb@fe3e0000 { 386 compatible = "generic-ohci"; 387 reg = <0x0 0xfe3e0000 0x0 0x20000>; 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 390 <&u2phy1>; 391 phys = <&u2phy1_host>; 392 phy-names = "usb"; 393 status = "disabled"; 394 }; 395 396 usbdrd3_0: usb@fe800000 { 397 compatible = "rockchip,rk3399-dwc3"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 404 clock-names = "ref_clk", "suspend_clk", 405 "bus_clk", "aclk_usb3_rksoc_axi_perf", 406 "aclk_usb3", "grf_clk"; 407 resets = <&cru SRST_A_USB3_OTG0>; 408 reset-names = "usb3-otg"; 409 status = "disabled"; 410 411 usbdrd_dwc3_0: usb@fe800000 { 412 compatible = "snps,dwc3"; 413 reg = <0x0 0xfe800000 0x0 0x100000>; 414 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 415 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 416 <&cru SCLK_USB3OTG0_SUSPEND>; 417 clock-names = "ref", "bus_early", "suspend"; 418 dr_mode = "otg"; 419 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 420 phy-names = "usb2-phy", "usb3-phy"; 421 phy_type = "utmi_wide"; 422 snps,dis_enblslpm_quirk; 423 snps,dis-u2-freeclk-exists-quirk; 424 snps,dis_u2_susphy_quirk; 425 snps,dis-del-phy-power-chg-quirk; 426 snps,dis-tx-ipgap-linecheck-quirk; 427 power-domains = <&power RK3399_PD_USB3>; 428 status = "disabled"; 429 }; 430 }; 431 432 usbdrd3_1: usb@fe900000 { 433 compatible = "rockchip,rk3399-dwc3"; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 438 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 439 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 440 clock-names = "ref_clk", "suspend_clk", 441 "bus_clk", "aclk_usb3_rksoc_axi_perf", 442 "aclk_usb3", "grf_clk"; 443 resets = <&cru SRST_A_USB3_OTG1>; 444 reset-names = "usb3-otg"; 445 status = "disabled"; 446 447 usbdrd_dwc3_1: usb@fe900000 { 448 compatible = "snps,dwc3"; 449 reg = <0x0 0xfe900000 0x0 0x100000>; 450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 451 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 452 <&cru SCLK_USB3OTG1_SUSPEND>; 453 clock-names = "ref", "bus_early", "suspend"; 454 dr_mode = "otg"; 455 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 456 phy-names = "usb2-phy", "usb3-phy"; 457 phy_type = "utmi_wide"; 458 snps,dis_enblslpm_quirk; 459 snps,dis-u2-freeclk-exists-quirk; 460 snps,dis_u2_susphy_quirk; 461 snps,dis-del-phy-power-chg-quirk; 462 snps,dis-tx-ipgap-linecheck-quirk; 463 power-domains = <&power RK3399_PD_USB3>; 464 status = "disabled"; 465 }; 466 }; 467 468 cdn_dp: dp@fec00000 { 469 compatible = "rockchip,rk3399-cdn-dp"; 470 reg = <0x0 0xfec00000 0x0 0x100000>; 471 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 472 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 473 assigned-clock-rates = <100000000>, <200000000>; 474 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 475 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 476 clock-names = "core-clk", "pclk", "spdif", "grf"; 477 phys = <&tcphy0_dp>, <&tcphy1_dp>; 478 power-domains = <&power RK3399_PD_HDCP>; 479 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 480 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 481 reset-names = "spdif", "dptx", "apb", "core"; 482 rockchip,grf = <&grf>; 483 #sound-dai-cells = <1>; 484 status = "disabled"; 485 486 ports { 487 dp_in: port { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 dp_in_vopb: endpoint@0 { 492 reg = <0>; 493 remote-endpoint = <&vopb_out_dp>; 494 }; 495 496 dp_in_vopl: endpoint@1 { 497 reg = <1>; 498 remote-endpoint = <&vopl_out_dp>; 499 }; 500 }; 501 }; 502 }; 503 504 gic: interrupt-controller@fee00000 { 505 compatible = "arm,gic-v3"; 506 #interrupt-cells = <4>; 507 #address-cells = <2>; 508 #size-cells = <2>; 509 ranges; 510 interrupt-controller; 511 512 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 513 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 514 <0x0 0xfff00000 0 0x10000>, /* GICC */ 515 <0x0 0xfff10000 0 0x10000>, /* GICH */ 516 <0x0 0xfff20000 0 0x10000>; /* GICV */ 517 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 518 its: interrupt-controller@fee20000 { 519 compatible = "arm,gic-v3-its"; 520 msi-controller; 521 #msi-cells = <1>; 522 reg = <0x0 0xfee20000 0x0 0x20000>; 523 }; 524 525 ppi-partitions { 526 ppi_cluster0: interrupt-partition-0 { 527 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 528 }; 529 530 ppi_cluster1: interrupt-partition-1 { 531 affinity = <&cpu_b0 &cpu_b1>; 532 }; 533 }; 534 }; 535 536 saradc: saradc@ff100000 { 537 compatible = "rockchip,rk3399-saradc"; 538 reg = <0x0 0xff100000 0x0 0x100>; 539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 540 #io-channel-cells = <1>; 541 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 542 clock-names = "saradc", "apb_pclk"; 543 resets = <&cru SRST_P_SARADC>; 544 reset-names = "saradc-apb"; 545 status = "disabled"; 546 }; 547 548 i2c1: i2c@ff110000 { 549 compatible = "rockchip,rk3399-i2c"; 550 reg = <0x0 0xff110000 0x0 0x1000>; 551 assigned-clocks = <&cru SCLK_I2C1>; 552 assigned-clock-rates = <200000000>; 553 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 554 clock-names = "i2c", "pclk"; 555 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c1_xfer>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 i2c2: i2c@ff120000 { 564 compatible = "rockchip,rk3399-i2c"; 565 reg = <0x0 0xff120000 0x0 0x1000>; 566 assigned-clocks = <&cru SCLK_I2C2>; 567 assigned-clock-rates = <200000000>; 568 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 569 clock-names = "i2c", "pclk"; 570 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&i2c2_xfer>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 i2c3: i2c@ff130000 { 579 compatible = "rockchip,rk3399-i2c"; 580 reg = <0x0 0xff130000 0x0 0x1000>; 581 assigned-clocks = <&cru SCLK_I2C3>; 582 assigned-clock-rates = <200000000>; 583 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 584 clock-names = "i2c", "pclk"; 585 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2c3_xfer>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 status = "disabled"; 591 }; 592 593 i2c5: i2c@ff140000 { 594 compatible = "rockchip,rk3399-i2c"; 595 reg = <0x0 0xff140000 0x0 0x1000>; 596 assigned-clocks = <&cru SCLK_I2C5>; 597 assigned-clock-rates = <200000000>; 598 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 599 clock-names = "i2c", "pclk"; 600 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&i2c5_xfer>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 status = "disabled"; 606 }; 607 608 i2c6: i2c@ff150000 { 609 compatible = "rockchip,rk3399-i2c"; 610 reg = <0x0 0xff150000 0x0 0x1000>; 611 assigned-clocks = <&cru SCLK_I2C6>; 612 assigned-clock-rates = <200000000>; 613 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 614 clock-names = "i2c", "pclk"; 615 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&i2c6_xfer>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 i2c7: i2c@ff160000 { 624 compatible = "rockchip,rk3399-i2c"; 625 reg = <0x0 0xff160000 0x0 0x1000>; 626 assigned-clocks = <&cru SCLK_I2C7>; 627 assigned-clock-rates = <200000000>; 628 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 629 clock-names = "i2c", "pclk"; 630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&i2c7_xfer>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 uart0: serial@ff180000 { 639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 640 reg = <0x0 0xff180000 0x0 0x100>; 641 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 642 clock-names = "baudclk", "apb_pclk"; 643 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 644 reg-shift = <2>; 645 reg-io-width = <4>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&uart0_xfer>; 648 status = "disabled"; 649 }; 650 651 uart1: serial@ff190000 { 652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 653 reg = <0x0 0xff190000 0x0 0x100>; 654 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 655 clock-names = "baudclk", "apb_pclk"; 656 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 657 reg-shift = <2>; 658 reg-io-width = <4>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&uart1_xfer>; 661 status = "disabled"; 662 }; 663 664 uart2: serial@ff1a0000 { 665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 666 reg = <0x0 0xff1a0000 0x0 0x100>; 667 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 668 clock-names = "baudclk", "apb_pclk"; 669 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 670 reg-shift = <2>; 671 reg-io-width = <4>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&uart2c_xfer>; 674 status = "disabled"; 675 }; 676 677 uart3: serial@ff1b0000 { 678 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 679 reg = <0x0 0xff1b0000 0x0 0x100>; 680 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 681 clock-names = "baudclk", "apb_pclk"; 682 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 683 reg-shift = <2>; 684 reg-io-width = <4>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&uart3_xfer>; 687 status = "disabled"; 688 }; 689 690 spi0: spi@ff1c0000 { 691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 692 reg = <0x0 0xff1c0000 0x0 0x1000>; 693 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 694 clock-names = "spiclk", "apb_pclk"; 695 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 696 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 697 dma-names = "tx", "rx"; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 spi1: spi@ff1d0000 { 706 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 707 reg = <0x0 0xff1d0000 0x0 0x1000>; 708 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 709 clock-names = "spiclk", "apb_pclk"; 710 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 711 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 712 dma-names = "tx", "rx"; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 spi2: spi@ff1e0000 { 721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 722 reg = <0x0 0xff1e0000 0x0 0x1000>; 723 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 724 clock-names = "spiclk", "apb_pclk"; 725 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 726 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 727 dma-names = "tx", "rx"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 spi4: spi@ff1f0000 { 736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 737 reg = <0x0 0xff1f0000 0x0 0x1000>; 738 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 739 clock-names = "spiclk", "apb_pclk"; 740 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 741 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 742 dma-names = "tx", "rx"; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 spi5: spi@ff200000 { 751 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 752 reg = <0x0 0xff200000 0x0 0x1000>; 753 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 754 clock-names = "spiclk", "apb_pclk"; 755 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 756 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 757 dma-names = "tx", "rx"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 760 power-domains = <&power RK3399_PD_SDIOAUDIO>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 thermal_zones: thermal-zones { 767 cpu_thermal: cpu { 768 polling-delay-passive = <100>; 769 polling-delay = <1000>; 770 771 thermal-sensors = <&tsadc 0>; 772 773 trips { 774 cpu_alert0: cpu_alert0 { 775 temperature = <70000>; 776 hysteresis = <2000>; 777 type = "passive"; 778 }; 779 cpu_alert1: cpu_alert1 { 780 temperature = <75000>; 781 hysteresis = <2000>; 782 type = "passive"; 783 }; 784 cpu_crit: cpu_crit { 785 temperature = <95000>; 786 hysteresis = <2000>; 787 type = "critical"; 788 }; 789 }; 790 791 cooling-maps { 792 map0 { 793 trip = <&cpu_alert0>; 794 cooling-device = 795 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 796 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 797 }; 798 map1 { 799 trip = <&cpu_alert1>; 800 cooling-device = 801 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 802 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 803 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 804 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 805 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 806 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 807 }; 808 }; 809 }; 810 811 gpu_thermal: gpu { 812 polling-delay-passive = <100>; 813 polling-delay = <1000>; 814 815 thermal-sensors = <&tsadc 1>; 816 817 trips { 818 gpu_alert0: gpu_alert0 { 819 temperature = <75000>; 820 hysteresis = <2000>; 821 type = "passive"; 822 }; 823 gpu_crit: gpu_crit { 824 temperature = <95000>; 825 hysteresis = <2000>; 826 type = "critical"; 827 }; 828 }; 829 830 cooling-maps { 831 map0 { 832 trip = <&gpu_alert0>; 833 cooling-device = 834 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 835 }; 836 }; 837 }; 838 }; 839 840 tsadc: tsadc@ff260000 { 841 compatible = "rockchip,rk3399-tsadc"; 842 reg = <0x0 0xff260000 0x0 0x100>; 843 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 844 assigned-clocks = <&cru SCLK_TSADC>; 845 assigned-clock-rates = <750000>; 846 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 847 clock-names = "tsadc", "apb_pclk"; 848 resets = <&cru SRST_TSADC>; 849 reset-names = "tsadc-apb"; 850 rockchip,grf = <&grf>; 851 rockchip,hw-tshut-temp = <95000>; 852 pinctrl-names = "init", "default", "sleep"; 853 pinctrl-0 = <&otp_pin>; 854 pinctrl-1 = <&otp_out>; 855 pinctrl-2 = <&otp_pin>; 856 #thermal-sensor-cells = <1>; 857 status = "disabled"; 858 }; 859 860 qos_emmc: qos@ffa58000 { 861 compatible = "syscon"; 862 reg = <0x0 0xffa58000 0x0 0x20>; 863 }; 864 865 qos_gmac: qos@ffa5c000 { 866 compatible = "syscon"; 867 reg = <0x0 0xffa5c000 0x0 0x20>; 868 }; 869 870 qos_pcie: qos@ffa60080 { 871 compatible = "syscon"; 872 reg = <0x0 0xffa60080 0x0 0x20>; 873 }; 874 875 qos_usb_host0: qos@ffa60100 { 876 compatible = "syscon"; 877 reg = <0x0 0xffa60100 0x0 0x20>; 878 }; 879 880 qos_usb_host1: qos@ffa60180 { 881 compatible = "syscon"; 882 reg = <0x0 0xffa60180 0x0 0x20>; 883 }; 884 885 qos_usb_otg0: qos@ffa70000 { 886 compatible = "syscon"; 887 reg = <0x0 0xffa70000 0x0 0x20>; 888 }; 889 890 qos_usb_otg1: qos@ffa70080 { 891 compatible = "syscon"; 892 reg = <0x0 0xffa70080 0x0 0x20>; 893 }; 894 895 qos_sd: qos@ffa74000 { 896 compatible = "syscon"; 897 reg = <0x0 0xffa74000 0x0 0x20>; 898 }; 899 900 qos_sdioaudio: qos@ffa76000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffa76000 0x0 0x20>; 903 }; 904 905 qos_hdcp: qos@ffa90000 { 906 compatible = "syscon"; 907 reg = <0x0 0xffa90000 0x0 0x20>; 908 }; 909 910 qos_iep: qos@ffa98000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffa98000 0x0 0x20>; 913 }; 914 915 qos_isp0_m0: qos@ffaa0000 { 916 compatible = "syscon"; 917 reg = <0x0 0xffaa0000 0x0 0x20>; 918 }; 919 920 qos_isp0_m1: qos@ffaa0080 { 921 compatible = "syscon"; 922 reg = <0x0 0xffaa0080 0x0 0x20>; 923 }; 924 925 qos_isp1_m0: qos@ffaa8000 { 926 compatible = "syscon"; 927 reg = <0x0 0xffaa8000 0x0 0x20>; 928 }; 929 930 qos_isp1_m1: qos@ffaa8080 { 931 compatible = "syscon"; 932 reg = <0x0 0xffaa8080 0x0 0x20>; 933 }; 934 935 qos_rga_r: qos@ffab0000 { 936 compatible = "syscon"; 937 reg = <0x0 0xffab0000 0x0 0x20>; 938 }; 939 940 qos_rga_w: qos@ffab0080 { 941 compatible = "syscon"; 942 reg = <0x0 0xffab0080 0x0 0x20>; 943 }; 944 945 qos_video_m0: qos@ffab8000 { 946 compatible = "syscon"; 947 reg = <0x0 0xffab8000 0x0 0x20>; 948 }; 949 950 qos_video_m1_r: qos@ffac0000 { 951 compatible = "syscon"; 952 reg = <0x0 0xffac0000 0x0 0x20>; 953 }; 954 955 qos_video_m1_w: qos@ffac0080 { 956 compatible = "syscon"; 957 reg = <0x0 0xffac0080 0x0 0x20>; 958 }; 959 960 qos_vop_big_r: qos@ffac8000 { 961 compatible = "syscon"; 962 reg = <0x0 0xffac8000 0x0 0x20>; 963 }; 964 965 qos_vop_big_w: qos@ffac8080 { 966 compatible = "syscon"; 967 reg = <0x0 0xffac8080 0x0 0x20>; 968 }; 969 970 qos_vop_little: qos@ffad0000 { 971 compatible = "syscon"; 972 reg = <0x0 0xffad0000 0x0 0x20>; 973 }; 974 975 qos_perihp: qos@ffad8080 { 976 compatible = "syscon"; 977 reg = <0x0 0xffad8080 0x0 0x20>; 978 }; 979 980 qos_gpu: qos@ffae0000 { 981 compatible = "syscon"; 982 reg = <0x0 0xffae0000 0x0 0x20>; 983 }; 984 985 pmu: power-management@ff310000 { 986 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 987 reg = <0x0 0xff310000 0x0 0x1000>; 988 989 /* 990 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 991 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 992 * Some of the power domains are grouped together for every 993 * voltage domain. 994 * The detail contents as below. 995 */ 996 power: power-controller { 997 compatible = "rockchip,rk3399-power-controller"; 998 #power-domain-cells = <1>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 /* These power domains are grouped by VD_CENTER */ 1003 power-domain@RK3399_PD_IEP { 1004 reg = <RK3399_PD_IEP>; 1005 clocks = <&cru ACLK_IEP>, 1006 <&cru HCLK_IEP>; 1007 pm_qos = <&qos_iep>; 1008 }; 1009 power-domain@RK3399_PD_RGA { 1010 reg = <RK3399_PD_RGA>; 1011 clocks = <&cru ACLK_RGA>, 1012 <&cru HCLK_RGA>; 1013 pm_qos = <&qos_rga_r>, 1014 <&qos_rga_w>; 1015 }; 1016 power-domain@RK3399_PD_VCODEC { 1017 reg = <RK3399_PD_VCODEC>; 1018 clocks = <&cru ACLK_VCODEC>, 1019 <&cru HCLK_VCODEC>; 1020 pm_qos = <&qos_video_m0>; 1021 }; 1022 power-domain@RK3399_PD_VDU { 1023 reg = <RK3399_PD_VDU>; 1024 clocks = <&cru ACLK_VDU>, 1025 <&cru HCLK_VDU>; 1026 pm_qos = <&qos_video_m1_r>, 1027 <&qos_video_m1_w>; 1028 }; 1029 1030 /* These power domains are grouped by VD_GPU */ 1031 power-domain@RK3399_PD_GPU { 1032 reg = <RK3399_PD_GPU>; 1033 clocks = <&cru ACLK_GPU>; 1034 pm_qos = <&qos_gpu>; 1035 }; 1036 1037 /* These power domains are grouped by VD_LOGIC */ 1038 power-domain@RK3399_PD_EDP { 1039 reg = <RK3399_PD_EDP>; 1040 clocks = <&cru PCLK_EDP_CTRL>; 1041 }; 1042 power-domain@RK3399_PD_EMMC { 1043 reg = <RK3399_PD_EMMC>; 1044 clocks = <&cru ACLK_EMMC>; 1045 pm_qos = <&qos_emmc>; 1046 }; 1047 power-domain@RK3399_PD_GMAC { 1048 reg = <RK3399_PD_GMAC>; 1049 clocks = <&cru ACLK_GMAC>, 1050 <&cru PCLK_GMAC>; 1051 pm_qos = <&qos_gmac>; 1052 }; 1053 power-domain@RK3399_PD_SD { 1054 reg = <RK3399_PD_SD>; 1055 clocks = <&cru HCLK_SDMMC>, 1056 <&cru SCLK_SDMMC>; 1057 pm_qos = <&qos_sd>; 1058 }; 1059 power-domain@RK3399_PD_SDIOAUDIO { 1060 reg = <RK3399_PD_SDIOAUDIO>; 1061 clocks = <&cru HCLK_SDIO>; 1062 pm_qos = <&qos_sdioaudio>; 1063 }; 1064 power-domain@RK3399_PD_TCPD0 { 1065 reg = <RK3399_PD_TCPD0>; 1066 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1067 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1068 }; 1069 power-domain@RK3399_PD_TCPD1 { 1070 reg = <RK3399_PD_TCPD1>; 1071 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1072 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1073 }; 1074 power-domain@RK3399_PD_USB3 { 1075 reg = <RK3399_PD_USB3>; 1076 clocks = <&cru ACLK_USB3>; 1077 pm_qos = <&qos_usb_otg0>, 1078 <&qos_usb_otg1>; 1079 }; 1080 power-domain@RK3399_PD_VIO { 1081 reg = <RK3399_PD_VIO>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 power-domain@RK3399_PD_HDCP { 1086 reg = <RK3399_PD_HDCP>; 1087 clocks = <&cru ACLK_HDCP>, 1088 <&cru HCLK_HDCP>, 1089 <&cru PCLK_HDCP>; 1090 pm_qos = <&qos_hdcp>; 1091 }; 1092 power-domain@RK3399_PD_ISP0 { 1093 reg = <RK3399_PD_ISP0>; 1094 clocks = <&cru ACLK_ISP0>, 1095 <&cru HCLK_ISP0>; 1096 pm_qos = <&qos_isp0_m0>, 1097 <&qos_isp0_m1>; 1098 }; 1099 power-domain@RK3399_PD_ISP1 { 1100 reg = <RK3399_PD_ISP1>; 1101 clocks = <&cru ACLK_ISP1>, 1102 <&cru HCLK_ISP1>; 1103 pm_qos = <&qos_isp1_m0>, 1104 <&qos_isp1_m1>; 1105 }; 1106 power-domain@RK3399_PD_VO { 1107 reg = <RK3399_PD_VO>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 1111 power-domain@RK3399_PD_VOPB { 1112 reg = <RK3399_PD_VOPB>; 1113 clocks = <&cru ACLK_VOP0>, 1114 <&cru HCLK_VOP0>; 1115 pm_qos = <&qos_vop_big_r>, 1116 <&qos_vop_big_w>; 1117 }; 1118 power-domain@RK3399_PD_VOPL { 1119 reg = <RK3399_PD_VOPL>; 1120 clocks = <&cru ACLK_VOP1>, 1121 <&cru HCLK_VOP1>; 1122 pm_qos = <&qos_vop_little>; 1123 }; 1124 }; 1125 }; 1126 }; 1127 }; 1128 1129 pmugrf: syscon@ff320000 { 1130 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1131 reg = <0x0 0xff320000 0x0 0x1000>; 1132 1133 pmu_io_domains: io-domains { 1134 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1135 status = "disabled"; 1136 }; 1137 }; 1138 1139 spi3: spi@ff350000 { 1140 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1141 reg = <0x0 0xff350000 0x0 0x1000>; 1142 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1143 clock-names = "spiclk", "apb_pclk"; 1144 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 uart4: serial@ff370000 { 1153 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1154 reg = <0x0 0xff370000 0x0 0x100>; 1155 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1156 clock-names = "baudclk", "apb_pclk"; 1157 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1158 reg-shift = <2>; 1159 reg-io-width = <4>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&uart4_xfer>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c0: i2c@ff3c0000 { 1166 compatible = "rockchip,rk3399-i2c"; 1167 reg = <0x0 0xff3c0000 0x0 0x1000>; 1168 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1169 assigned-clock-rates = <200000000>; 1170 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1171 clock-names = "i2c", "pclk"; 1172 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&i2c0_xfer>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 i2c4: i2c@ff3d0000 { 1181 compatible = "rockchip,rk3399-i2c"; 1182 reg = <0x0 0xff3d0000 0x0 0x1000>; 1183 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1184 assigned-clock-rates = <200000000>; 1185 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1186 clock-names = "i2c", "pclk"; 1187 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&i2c4_xfer>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c8: i2c@ff3e0000 { 1196 compatible = "rockchip,rk3399-i2c"; 1197 reg = <0x0 0xff3e0000 0x0 0x1000>; 1198 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1199 assigned-clock-rates = <200000000>; 1200 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1201 clock-names = "i2c", "pclk"; 1202 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&i2c8_xfer>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 1210 pwm0: pwm@ff420000 { 1211 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1212 reg = <0x0 0xff420000 0x0 0x10>; 1213 #pwm-cells = <3>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&pwm0_pin>; 1216 clocks = <&pmucru PCLK_RKPWM_PMU>; 1217 clock-names = "pwm"; 1218 status = "disabled"; 1219 }; 1220 1221 pwm1: pwm@ff420010 { 1222 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1223 reg = <0x0 0xff420010 0x0 0x10>; 1224 #pwm-cells = <3>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&pwm1_pin>; 1227 clocks = <&pmucru PCLK_RKPWM_PMU>; 1228 clock-names = "pwm"; 1229 status = "disabled"; 1230 }; 1231 1232 pwm2: pwm@ff420020 { 1233 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1234 reg = <0x0 0xff420020 0x0 0x10>; 1235 #pwm-cells = <3>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&pwm2_pin>; 1238 clocks = <&pmucru PCLK_RKPWM_PMU>; 1239 clock-names = "pwm"; 1240 status = "disabled"; 1241 }; 1242 1243 pwm3: pwm@ff420030 { 1244 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1245 reg = <0x0 0xff420030 0x0 0x10>; 1246 #pwm-cells = <3>; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&pwm3a_pin>; 1249 clocks = <&pmucru PCLK_RKPWM_PMU>; 1250 clock-names = "pwm"; 1251 status = "disabled"; 1252 }; 1253 1254 vpu: video-codec@ff650000 { 1255 compatible = "rockchip,rk3399-vpu"; 1256 reg = <0x0 0xff650000 0x0 0x800>; 1257 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1258 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1259 interrupt-names = "vepu", "vdpu"; 1260 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1261 clock-names = "aclk", "hclk"; 1262 iommus = <&vpu_mmu>; 1263 power-domains = <&power RK3399_PD_VCODEC>; 1264 }; 1265 1266 vpu_mmu: iommu@ff650800 { 1267 compatible = "rockchip,iommu"; 1268 reg = <0x0 0xff650800 0x0 0x40>; 1269 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1270 interrupt-names = "vpu_mmu"; 1271 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1272 clock-names = "aclk", "iface"; 1273 #iommu-cells = <0>; 1274 power-domains = <&power RK3399_PD_VCODEC>; 1275 }; 1276 1277 vdec: video-codec@ff660000 { 1278 compatible = "rockchip,rk3399-vdec"; 1279 reg = <0x0 0xff660000 0x0 0x400>; 1280 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1281 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1282 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1283 clock-names = "axi", "ahb", "cabac", "core"; 1284 iommus = <&vdec_mmu>; 1285 power-domains = <&power RK3399_PD_VDU>; 1286 }; 1287 1288 vdec_mmu: iommu@ff660480 { 1289 compatible = "rockchip,iommu"; 1290 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1291 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1292 interrupt-names = "vdec_mmu"; 1293 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1294 clock-names = "aclk", "iface"; 1295 power-domains = <&power RK3399_PD_VDU>; 1296 #iommu-cells = <0>; 1297 }; 1298 1299 iep_mmu: iommu@ff670800 { 1300 compatible = "rockchip,iommu"; 1301 reg = <0x0 0xff670800 0x0 0x40>; 1302 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1303 interrupt-names = "iep_mmu"; 1304 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1305 clock-names = "aclk", "iface"; 1306 #iommu-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 rga: rga@ff680000 { 1311 compatible = "rockchip,rk3399-rga"; 1312 reg = <0x0 0xff680000 0x0 0x10000>; 1313 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1314 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1315 clock-names = "aclk", "hclk", "sclk"; 1316 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1317 reset-names = "core", "axi", "ahb"; 1318 power-domains = <&power RK3399_PD_RGA>; 1319 }; 1320 1321 efuse0: efuse@ff690000 { 1322 compatible = "rockchip,rk3399-efuse"; 1323 reg = <0x0 0xff690000 0x0 0x80>; 1324 #address-cells = <1>; 1325 #size-cells = <1>; 1326 clocks = <&cru PCLK_EFUSE1024NS>; 1327 clock-names = "pclk_efuse"; 1328 1329 /* Data cells */ 1330 cpu_id: cpu-id@7 { 1331 reg = <0x07 0x10>; 1332 }; 1333 cpub_leakage: cpu-leakage@17 { 1334 reg = <0x17 0x1>; 1335 }; 1336 gpu_leakage: gpu-leakage@18 { 1337 reg = <0x18 0x1>; 1338 }; 1339 center_leakage: center-leakage@19 { 1340 reg = <0x19 0x1>; 1341 }; 1342 cpul_leakage: cpu-leakage@1a { 1343 reg = <0x1a 0x1>; 1344 }; 1345 logic_leakage: logic-leakage@1b { 1346 reg = <0x1b 0x1>; 1347 }; 1348 wafer_info: wafer-info@1c { 1349 reg = <0x1c 0x1>; 1350 }; 1351 }; 1352 1353 pmucru: pmu-clock-controller@ff750000 { 1354 compatible = "rockchip,rk3399-pmucru"; 1355 reg = <0x0 0xff750000 0x0 0x1000>; 1356 rockchip,grf = <&pmugrf>; 1357 #clock-cells = <1>; 1358 #reset-cells = <1>; 1359 assigned-clocks = <&pmucru PLL_PPLL>; 1360 assigned-clock-rates = <676000000>; 1361 }; 1362 1363 cru: clock-controller@ff760000 { 1364 compatible = "rockchip,rk3399-cru"; 1365 reg = <0x0 0xff760000 0x0 0x1000>; 1366 rockchip,grf = <&grf>; 1367 #clock-cells = <1>; 1368 #reset-cells = <1>; 1369 assigned-clocks = 1370 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1371 <&cru PLL_NPLL>, 1372 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1373 <&cru PCLK_PERIHP>, 1374 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1375 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1376 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1377 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1378 <&cru ACLK_GIC_PRE>, 1379 <&cru PCLK_DDR>; 1380 assigned-clock-rates = 1381 <594000000>, <800000000>, 1382 <1000000000>, 1383 <150000000>, <75000000>, 1384 <37500000>, 1385 <100000000>, <100000000>, 1386 <50000000>, <600000000>, 1387 <100000000>, <50000000>, 1388 <400000000>, <400000000>, 1389 <200000000>, 1390 <200000000>; 1391 }; 1392 1393 grf: syscon@ff770000 { 1394 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1395 reg = <0x0 0xff770000 0x0 0x10000>; 1396 #address-cells = <1>; 1397 #size-cells = <1>; 1398 1399 io_domains: io-domains { 1400 compatible = "rockchip,rk3399-io-voltage-domain"; 1401 status = "disabled"; 1402 }; 1403 1404 mipi_dphy_rx0: mipi-dphy-rx0 { 1405 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1406 clocks = <&cru SCLK_MIPIDPHY_REF>, 1407 <&cru SCLK_DPHY_RX0_CFG>, 1408 <&cru PCLK_VIO_GRF>; 1409 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1410 power-domains = <&power RK3399_PD_VIO>; 1411 #phy-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 u2phy0: usb2-phy@e450 { 1416 compatible = "rockchip,rk3399-usb2phy"; 1417 reg = <0xe450 0x10>; 1418 clocks = <&cru SCLK_USB2PHY0_REF>; 1419 clock-names = "phyclk"; 1420 #clock-cells = <0>; 1421 clock-output-names = "clk_usbphy0_480m"; 1422 status = "disabled"; 1423 1424 u2phy0_host: host-port { 1425 #phy-cells = <0>; 1426 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1427 interrupt-names = "linestate"; 1428 status = "disabled"; 1429 }; 1430 1431 u2phy0_otg: otg-port { 1432 #phy-cells = <0>; 1433 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1434 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1435 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1436 interrupt-names = "otg-bvalid", "otg-id", 1437 "linestate"; 1438 status = "disabled"; 1439 }; 1440 }; 1441 1442 u2phy1: usb2-phy@e460 { 1443 compatible = "rockchip,rk3399-usb2phy"; 1444 reg = <0xe460 0x10>; 1445 clocks = <&cru SCLK_USB2PHY1_REF>; 1446 clock-names = "phyclk"; 1447 #clock-cells = <0>; 1448 clock-output-names = "clk_usbphy1_480m"; 1449 status = "disabled"; 1450 1451 u2phy1_host: host-port { 1452 #phy-cells = <0>; 1453 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1454 interrupt-names = "linestate"; 1455 status = "disabled"; 1456 }; 1457 1458 u2phy1_otg: otg-port { 1459 #phy-cells = <0>; 1460 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1461 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1462 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1463 interrupt-names = "otg-bvalid", "otg-id", 1464 "linestate"; 1465 status = "disabled"; 1466 }; 1467 }; 1468 1469 emmc_phy: phy@f780 { 1470 compatible = "rockchip,rk3399-emmc-phy"; 1471 reg = <0xf780 0x24>; 1472 clocks = <&sdhci>; 1473 clock-names = "emmcclk"; 1474 drive-impedance-ohm = <50>; 1475 #phy-cells = <0>; 1476 status = "disabled"; 1477 }; 1478 1479 pcie_phy: pcie-phy { 1480 compatible = "rockchip,rk3399-pcie-phy"; 1481 clocks = <&cru SCLK_PCIEPHY_REF>; 1482 clock-names = "refclk"; 1483 #phy-cells = <1>; 1484 resets = <&cru SRST_PCIEPHY>; 1485 reset-names = "phy"; 1486 status = "disabled"; 1487 }; 1488 }; 1489 1490 tcphy0: phy@ff7c0000 { 1491 compatible = "rockchip,rk3399-typec-phy"; 1492 reg = <0x0 0xff7c0000 0x0 0x40000>; 1493 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1494 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1495 clock-names = "tcpdcore", "tcpdphy-ref"; 1496 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1497 assigned-clock-rates = <50000000>; 1498 power-domains = <&power RK3399_PD_TCPD0>; 1499 resets = <&cru SRST_UPHY0>, 1500 <&cru SRST_UPHY0_PIPE_L00>, 1501 <&cru SRST_P_UPHY0_TCPHY>; 1502 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1503 rockchip,grf = <&grf>; 1504 status = "disabled"; 1505 1506 tcphy0_dp: dp-port { 1507 #phy-cells = <0>; 1508 }; 1509 1510 tcphy0_usb3: usb3-port { 1511 #phy-cells = <0>; 1512 }; 1513 }; 1514 1515 tcphy1: phy@ff800000 { 1516 compatible = "rockchip,rk3399-typec-phy"; 1517 reg = <0x0 0xff800000 0x0 0x40000>; 1518 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1519 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1520 clock-names = "tcpdcore", "tcpdphy-ref"; 1521 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1522 assigned-clock-rates = <50000000>; 1523 power-domains = <&power RK3399_PD_TCPD1>; 1524 resets = <&cru SRST_UPHY1>, 1525 <&cru SRST_UPHY1_PIPE_L00>, 1526 <&cru SRST_P_UPHY1_TCPHY>; 1527 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1528 rockchip,grf = <&grf>; 1529 status = "disabled"; 1530 1531 tcphy1_dp: dp-port { 1532 #phy-cells = <0>; 1533 }; 1534 1535 tcphy1_usb3: usb3-port { 1536 #phy-cells = <0>; 1537 }; 1538 }; 1539 1540 watchdog@ff848000 { 1541 compatible = "snps,dw-wdt"; 1542 reg = <0x0 0xff848000 0x0 0x100>; 1543 clocks = <&cru PCLK_WDT>; 1544 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1545 }; 1546 1547 rktimer: rktimer@ff850000 { 1548 compatible = "rockchip,rk3399-timer"; 1549 reg = <0x0 0xff850000 0x0 0x1000>; 1550 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1551 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1552 clock-names = "pclk", "timer"; 1553 }; 1554 1555 spdif: spdif@ff870000 { 1556 compatible = "rockchip,rk3399-spdif"; 1557 reg = <0x0 0xff870000 0x0 0x1000>; 1558 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1559 dmas = <&dmac_bus 7>; 1560 dma-names = "tx"; 1561 clock-names = "mclk", "hclk"; 1562 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&spdif_bus>; 1565 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1566 #sound-dai-cells = <0>; 1567 status = "disabled"; 1568 }; 1569 1570 i2s0: i2s@ff880000 { 1571 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1572 reg = <0x0 0xff880000 0x0 0x1000>; 1573 rockchip,grf = <&grf>; 1574 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1575 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1576 dma-names = "tx", "rx"; 1577 clock-names = "i2s_clk", "i2s_hclk"; 1578 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1579 pinctrl-names = "default"; 1580 pinctrl-0 = <&i2s0_8ch_bus>; 1581 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1582 #sound-dai-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 i2s1: i2s@ff890000 { 1587 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1588 reg = <0x0 0xff890000 0x0 0x1000>; 1589 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1590 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1591 dma-names = "tx", "rx"; 1592 clock-names = "i2s_clk", "i2s_hclk"; 1593 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&i2s1_2ch_bus>; 1596 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1597 #sound-dai-cells = <0>; 1598 status = "disabled"; 1599 }; 1600 1601 i2s2: i2s@ff8a0000 { 1602 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1603 reg = <0x0 0xff8a0000 0x0 0x1000>; 1604 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1605 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1606 dma-names = "tx", "rx"; 1607 clock-names = "i2s_clk", "i2s_hclk"; 1608 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1609 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1610 #sound-dai-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 vopl: vop@ff8f0000 { 1615 compatible = "rockchip,rk3399-vop-lit"; 1616 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1617 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1618 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1619 assigned-clock-rates = <400000000>, <100000000>; 1620 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1621 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1622 iommus = <&vopl_mmu>; 1623 power-domains = <&power RK3399_PD_VOPL>; 1624 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1625 reset-names = "axi", "ahb", "dclk"; 1626 status = "disabled"; 1627 1628 vopl_out: port { 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 1632 vopl_out_mipi: endpoint@0 { 1633 reg = <0>; 1634 remote-endpoint = <&mipi_in_vopl>; 1635 }; 1636 1637 vopl_out_edp: endpoint@1 { 1638 reg = <1>; 1639 remote-endpoint = <&edp_in_vopl>; 1640 }; 1641 1642 vopl_out_hdmi: endpoint@2 { 1643 reg = <2>; 1644 remote-endpoint = <&hdmi_in_vopl>; 1645 }; 1646 1647 vopl_out_mipi1: endpoint@3 { 1648 reg = <3>; 1649 remote-endpoint = <&mipi1_in_vopl>; 1650 }; 1651 1652 vopl_out_dp: endpoint@4 { 1653 reg = <4>; 1654 remote-endpoint = <&dp_in_vopl>; 1655 }; 1656 }; 1657 }; 1658 1659 vopl_mmu: iommu@ff8f3f00 { 1660 compatible = "rockchip,iommu"; 1661 reg = <0x0 0xff8f3f00 0x0 0x100>; 1662 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1663 interrupt-names = "vopl_mmu"; 1664 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1665 clock-names = "aclk", "iface"; 1666 power-domains = <&power RK3399_PD_VOPL>; 1667 #iommu-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 vopb: vop@ff900000 { 1672 compatible = "rockchip,rk3399-vop-big"; 1673 reg = <0x0 0xff900000 0x0 0x3efc>; 1674 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1675 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1676 assigned-clock-rates = <400000000>, <100000000>; 1677 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1678 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1679 iommus = <&vopb_mmu>; 1680 power-domains = <&power RK3399_PD_VOPB>; 1681 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1682 reset-names = "axi", "ahb", "dclk"; 1683 status = "disabled"; 1684 1685 vopb_out: port { 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 1689 vopb_out_edp: endpoint@0 { 1690 reg = <0>; 1691 remote-endpoint = <&edp_in_vopb>; 1692 }; 1693 1694 vopb_out_mipi: endpoint@1 { 1695 reg = <1>; 1696 remote-endpoint = <&mipi_in_vopb>; 1697 }; 1698 1699 vopb_out_hdmi: endpoint@2 { 1700 reg = <2>; 1701 remote-endpoint = <&hdmi_in_vopb>; 1702 }; 1703 1704 vopb_out_mipi1: endpoint@3 { 1705 reg = <3>; 1706 remote-endpoint = <&mipi1_in_vopb>; 1707 }; 1708 1709 vopb_out_dp: endpoint@4 { 1710 reg = <4>; 1711 remote-endpoint = <&dp_in_vopb>; 1712 }; 1713 }; 1714 }; 1715 1716 vopb_mmu: iommu@ff903f00 { 1717 compatible = "rockchip,iommu"; 1718 reg = <0x0 0xff903f00 0x0 0x100>; 1719 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1720 interrupt-names = "vopb_mmu"; 1721 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1722 clock-names = "aclk", "iface"; 1723 power-domains = <&power RK3399_PD_VOPB>; 1724 #iommu-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 isp0_mmu: iommu@ff914000 { 1729 compatible = "rockchip,iommu"; 1730 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1732 interrupt-names = "isp0_mmu"; 1733 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1734 clock-names = "aclk", "iface"; 1735 #iommu-cells = <0>; 1736 power-domains = <&power RK3399_PD_ISP0>; 1737 rockchip,disable-mmu-reset; 1738 }; 1739 1740 isp1_mmu: iommu@ff924000 { 1741 compatible = "rockchip,iommu"; 1742 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1743 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1744 interrupt-names = "isp1_mmu"; 1745 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1746 clock-names = "aclk", "iface"; 1747 #iommu-cells = <0>; 1748 power-domains = <&power RK3399_PD_ISP1>; 1749 rockchip,disable-mmu-reset; 1750 }; 1751 1752 hdmi_sound: hdmi-sound { 1753 compatible = "simple-audio-card"; 1754 simple-audio-card,format = "i2s"; 1755 simple-audio-card,mclk-fs = <256>; 1756 simple-audio-card,name = "hdmi-sound"; 1757 status = "disabled"; 1758 1759 simple-audio-card,cpu { 1760 sound-dai = <&i2s2>; 1761 }; 1762 simple-audio-card,codec { 1763 sound-dai = <&hdmi>; 1764 }; 1765 }; 1766 1767 hdmi: hdmi@ff940000 { 1768 compatible = "rockchip,rk3399-dw-hdmi"; 1769 reg = <0x0 0xff940000 0x0 0x20000>; 1770 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1771 clocks = <&cru PCLK_HDMI_CTRL>, 1772 <&cru SCLK_HDMI_SFR>, 1773 <&cru SCLK_HDMI_CEC>, 1774 <&cru PCLK_VIO_GRF>, 1775 <&cru PLL_VPLL>; 1776 clock-names = "iahb", "isfr", "cec", "grf", "vpll"; 1777 power-domains = <&power RK3399_PD_HDCP>; 1778 reg-io-width = <4>; 1779 rockchip,grf = <&grf>; 1780 #sound-dai-cells = <0>; 1781 status = "disabled"; 1782 1783 ports { 1784 hdmi_in: port { 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 1788 hdmi_in_vopb: endpoint@0 { 1789 reg = <0>; 1790 remote-endpoint = <&vopb_out_hdmi>; 1791 }; 1792 hdmi_in_vopl: endpoint@1 { 1793 reg = <1>; 1794 remote-endpoint = <&vopl_out_hdmi>; 1795 }; 1796 }; 1797 }; 1798 }; 1799 1800 mipi_dsi: mipi@ff960000 { 1801 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1802 reg = <0x0 0xff960000 0x0 0x8000>; 1803 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1804 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1805 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1806 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1807 power-domains = <&power RK3399_PD_VIO>; 1808 resets = <&cru SRST_P_MIPI_DSI0>; 1809 reset-names = "apb"; 1810 rockchip,grf = <&grf>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 1815 ports { 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 1819 mipi_in: port@0 { 1820 reg = <0>; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 1824 mipi_in_vopb: endpoint@0 { 1825 reg = <0>; 1826 remote-endpoint = <&vopb_out_mipi>; 1827 }; 1828 mipi_in_vopl: endpoint@1 { 1829 reg = <1>; 1830 remote-endpoint = <&vopl_out_mipi>; 1831 }; 1832 }; 1833 }; 1834 }; 1835 1836 mipi_dsi1: mipi@ff968000 { 1837 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1838 reg = <0x0 0xff968000 0x0 0x8000>; 1839 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1840 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1841 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1842 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1843 power-domains = <&power RK3399_PD_VIO>; 1844 resets = <&cru SRST_P_MIPI_DSI1>; 1845 reset-names = "apb"; 1846 rockchip,grf = <&grf>; 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 status = "disabled"; 1850 1851 ports { 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 1855 mipi1_in: port@0 { 1856 reg = <0>; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 1860 mipi1_in_vopb: endpoint@0 { 1861 reg = <0>; 1862 remote-endpoint = <&vopb_out_mipi1>; 1863 }; 1864 1865 mipi1_in_vopl: endpoint@1 { 1866 reg = <1>; 1867 remote-endpoint = <&vopl_out_mipi1>; 1868 }; 1869 }; 1870 }; 1871 }; 1872 1873 edp: edp@ff970000 { 1874 compatible = "rockchip,rk3399-edp"; 1875 reg = <0x0 0xff970000 0x0 0x8000>; 1876 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1877 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1878 clock-names = "dp", "pclk", "grf"; 1879 pinctrl-names = "default"; 1880 pinctrl-0 = <&edp_hpd>; 1881 power-domains = <&power RK3399_PD_EDP>; 1882 resets = <&cru SRST_P_EDP_CTRL>; 1883 reset-names = "dp"; 1884 rockchip,grf = <&grf>; 1885 status = "disabled"; 1886 1887 ports { 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 edp_in: port@0 { 1891 reg = <0>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 1895 edp_in_vopb: endpoint@0 { 1896 reg = <0>; 1897 remote-endpoint = <&vopb_out_edp>; 1898 }; 1899 1900 edp_in_vopl: endpoint@1 { 1901 reg = <1>; 1902 remote-endpoint = <&vopl_out_edp>; 1903 }; 1904 }; 1905 }; 1906 }; 1907 1908 gpu: gpu@ff9a0000 { 1909 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1910 reg = <0x0 0xff9a0000 0x0 0x10000>; 1911 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1912 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1913 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1914 interrupt-names = "job", "mmu", "gpu"; 1915 clocks = <&cru ACLK_GPU>; 1916 #cooling-cells = <2>; 1917 power-domains = <&power RK3399_PD_GPU>; 1918 status = "disabled"; 1919 }; 1920 1921 pinctrl: pinctrl { 1922 compatible = "rockchip,rk3399-pinctrl"; 1923 rockchip,grf = <&grf>; 1924 rockchip,pmu = <&pmugrf>; 1925 #address-cells = <2>; 1926 #size-cells = <2>; 1927 ranges; 1928 1929 gpio0: gpio0@ff720000 { 1930 compatible = "rockchip,gpio-bank"; 1931 reg = <0x0 0xff720000 0x0 0x100>; 1932 clocks = <&pmucru PCLK_GPIO0_PMU>; 1933 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1934 1935 gpio-controller; 1936 #gpio-cells = <0x2>; 1937 1938 interrupt-controller; 1939 #interrupt-cells = <0x2>; 1940 }; 1941 1942 gpio1: gpio1@ff730000 { 1943 compatible = "rockchip,gpio-bank"; 1944 reg = <0x0 0xff730000 0x0 0x100>; 1945 clocks = <&pmucru PCLK_GPIO1_PMU>; 1946 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1947 1948 gpio-controller; 1949 #gpio-cells = <0x2>; 1950 1951 interrupt-controller; 1952 #interrupt-cells = <0x2>; 1953 }; 1954 1955 gpio2: gpio2@ff780000 { 1956 compatible = "rockchip,gpio-bank"; 1957 reg = <0x0 0xff780000 0x0 0x100>; 1958 clocks = <&cru PCLK_GPIO2>; 1959 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1960 1961 gpio-controller; 1962 #gpio-cells = <0x2>; 1963 1964 interrupt-controller; 1965 #interrupt-cells = <0x2>; 1966 }; 1967 1968 gpio3: gpio3@ff788000 { 1969 compatible = "rockchip,gpio-bank"; 1970 reg = <0x0 0xff788000 0x0 0x100>; 1971 clocks = <&cru PCLK_GPIO3>; 1972 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1973 1974 gpio-controller; 1975 #gpio-cells = <0x2>; 1976 1977 interrupt-controller; 1978 #interrupt-cells = <0x2>; 1979 }; 1980 1981 gpio4: gpio4@ff790000 { 1982 compatible = "rockchip,gpio-bank"; 1983 reg = <0x0 0xff790000 0x0 0x100>; 1984 clocks = <&cru PCLK_GPIO4>; 1985 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1986 1987 gpio-controller; 1988 #gpio-cells = <0x2>; 1989 1990 interrupt-controller; 1991 #interrupt-cells = <0x2>; 1992 }; 1993 1994 pcfg_pull_up: pcfg-pull-up { 1995 bias-pull-up; 1996 }; 1997 1998 pcfg_pull_down: pcfg-pull-down { 1999 bias-pull-down; 2000 }; 2001 2002 pcfg_pull_none: pcfg-pull-none { 2003 bias-disable; 2004 }; 2005 2006 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2007 bias-disable; 2008 drive-strength = <12>; 2009 }; 2010 2011 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2012 bias-disable; 2013 drive-strength = <13>; 2014 }; 2015 2016 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2017 bias-disable; 2018 drive-strength = <18>; 2019 }; 2020 2021 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2022 bias-disable; 2023 drive-strength = <20>; 2024 }; 2025 2026 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2027 bias-pull-up; 2028 drive-strength = <2>; 2029 }; 2030 2031 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2032 bias-pull-up; 2033 drive-strength = <8>; 2034 }; 2035 2036 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2037 bias-pull-up; 2038 drive-strength = <18>; 2039 }; 2040 2041 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2042 bias-pull-up; 2043 drive-strength = <20>; 2044 }; 2045 2046 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2047 bias-pull-down; 2048 drive-strength = <4>; 2049 }; 2050 2051 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2052 bias-pull-down; 2053 drive-strength = <8>; 2054 }; 2055 2056 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2057 bias-pull-down; 2058 drive-strength = <12>; 2059 }; 2060 2061 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2062 bias-pull-down; 2063 drive-strength = <18>; 2064 }; 2065 2066 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2067 bias-pull-down; 2068 drive-strength = <20>; 2069 }; 2070 2071 pcfg_output_high: pcfg-output-high { 2072 output-high; 2073 }; 2074 2075 pcfg_output_low: pcfg-output-low { 2076 output-low; 2077 }; 2078 2079 clock { 2080 clk_32k: clk-32k { 2081 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2082 }; 2083 }; 2084 2085 edp { 2086 edp_hpd: edp-hpd { 2087 rockchip,pins = 2088 <4 RK_PC7 2 &pcfg_pull_none>; 2089 }; 2090 }; 2091 2092 gmac { 2093 rgmii_pins: rgmii-pins { 2094 rockchip,pins = 2095 /* mac_txclk */ 2096 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2097 /* mac_rxclk */ 2098 <3 RK_PB6 1 &pcfg_pull_none>, 2099 /* mac_mdio */ 2100 <3 RK_PB5 1 &pcfg_pull_none>, 2101 /* mac_txen */ 2102 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2103 /* mac_clk */ 2104 <3 RK_PB3 1 &pcfg_pull_none>, 2105 /* mac_rxdv */ 2106 <3 RK_PB1 1 &pcfg_pull_none>, 2107 /* mac_mdc */ 2108 <3 RK_PB0 1 &pcfg_pull_none>, 2109 /* mac_rxd1 */ 2110 <3 RK_PA7 1 &pcfg_pull_none>, 2111 /* mac_rxd0 */ 2112 <3 RK_PA6 1 &pcfg_pull_none>, 2113 /* mac_txd1 */ 2114 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2115 /* mac_txd0 */ 2116 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2117 /* mac_rxd3 */ 2118 <3 RK_PA3 1 &pcfg_pull_none>, 2119 /* mac_rxd2 */ 2120 <3 RK_PA2 1 &pcfg_pull_none>, 2121 /* mac_txd3 */ 2122 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2123 /* mac_txd2 */ 2124 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2125 }; 2126 2127 rmii_pins: rmii-pins { 2128 rockchip,pins = 2129 /* mac_mdio */ 2130 <3 RK_PB5 1 &pcfg_pull_none>, 2131 /* mac_txen */ 2132 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2133 /* mac_clk */ 2134 <3 RK_PB3 1 &pcfg_pull_none>, 2135 /* mac_rxer */ 2136 <3 RK_PB2 1 &pcfg_pull_none>, 2137 /* mac_rxdv */ 2138 <3 RK_PB1 1 &pcfg_pull_none>, 2139 /* mac_mdc */ 2140 <3 RK_PB0 1 &pcfg_pull_none>, 2141 /* mac_rxd1 */ 2142 <3 RK_PA7 1 &pcfg_pull_none>, 2143 /* mac_rxd0 */ 2144 <3 RK_PA6 1 &pcfg_pull_none>, 2145 /* mac_txd1 */ 2146 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2147 /* mac_txd0 */ 2148 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2149 }; 2150 }; 2151 2152 i2c0 { 2153 i2c0_xfer: i2c0-xfer { 2154 rockchip,pins = 2155 <1 RK_PB7 2 &pcfg_pull_none>, 2156 <1 RK_PC0 2 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 i2c1 { 2161 i2c1_xfer: i2c1-xfer { 2162 rockchip,pins = 2163 <4 RK_PA2 1 &pcfg_pull_none>, 2164 <4 RK_PA1 1 &pcfg_pull_none>; 2165 }; 2166 }; 2167 2168 i2c2 { 2169 i2c2_xfer: i2c2-xfer { 2170 rockchip,pins = 2171 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2172 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2173 }; 2174 }; 2175 2176 i2c3 { 2177 i2c3_xfer: i2c3-xfer { 2178 rockchip,pins = 2179 <4 RK_PC1 1 &pcfg_pull_none>, 2180 <4 RK_PC0 1 &pcfg_pull_none>; 2181 }; 2182 }; 2183 2184 i2c4 { 2185 i2c4_xfer: i2c4-xfer { 2186 rockchip,pins = 2187 <1 RK_PB4 1 &pcfg_pull_none>, 2188 <1 RK_PB3 1 &pcfg_pull_none>; 2189 }; 2190 }; 2191 2192 i2c5 { 2193 i2c5_xfer: i2c5-xfer { 2194 rockchip,pins = 2195 <3 RK_PB3 2 &pcfg_pull_none>, 2196 <3 RK_PB2 2 &pcfg_pull_none>; 2197 }; 2198 }; 2199 2200 i2c6 { 2201 i2c6_xfer: i2c6-xfer { 2202 rockchip,pins = 2203 <2 RK_PB2 2 &pcfg_pull_none>, 2204 <2 RK_PB1 2 &pcfg_pull_none>; 2205 }; 2206 }; 2207 2208 i2c7 { 2209 i2c7_xfer: i2c7-xfer { 2210 rockchip,pins = 2211 <2 RK_PB0 2 &pcfg_pull_none>, 2212 <2 RK_PA7 2 &pcfg_pull_none>; 2213 }; 2214 }; 2215 2216 i2c8 { 2217 i2c8_xfer: i2c8-xfer { 2218 rockchip,pins = 2219 <1 RK_PC5 1 &pcfg_pull_none>, 2220 <1 RK_PC4 1 &pcfg_pull_none>; 2221 }; 2222 }; 2223 2224 i2s0 { 2225 i2s0_2ch_bus: i2s0-2ch-bus { 2226 rockchip,pins = 2227 <3 RK_PD0 1 &pcfg_pull_none>, 2228 <3 RK_PD1 1 &pcfg_pull_none>, 2229 <3 RK_PD2 1 &pcfg_pull_none>, 2230 <3 RK_PD3 1 &pcfg_pull_none>, 2231 <3 RK_PD7 1 &pcfg_pull_none>, 2232 <4 RK_PA0 1 &pcfg_pull_none>; 2233 }; 2234 2235 i2s0_8ch_bus: i2s0-8ch-bus { 2236 rockchip,pins = 2237 <3 RK_PD0 1 &pcfg_pull_none>, 2238 <3 RK_PD1 1 &pcfg_pull_none>, 2239 <3 RK_PD2 1 &pcfg_pull_none>, 2240 <3 RK_PD3 1 &pcfg_pull_none>, 2241 <3 RK_PD4 1 &pcfg_pull_none>, 2242 <3 RK_PD5 1 &pcfg_pull_none>, 2243 <3 RK_PD6 1 &pcfg_pull_none>, 2244 <3 RK_PD7 1 &pcfg_pull_none>, 2245 <4 RK_PA0 1 &pcfg_pull_none>; 2246 }; 2247 }; 2248 2249 i2s1 { 2250 i2s1_2ch_bus: i2s1-2ch-bus { 2251 rockchip,pins = 2252 <4 RK_PA3 1 &pcfg_pull_none>, 2253 <4 RK_PA4 1 &pcfg_pull_none>, 2254 <4 RK_PA5 1 &pcfg_pull_none>, 2255 <4 RK_PA6 1 &pcfg_pull_none>, 2256 <4 RK_PA7 1 &pcfg_pull_none>; 2257 }; 2258 }; 2259 2260 sdio0 { 2261 sdio0_bus1: sdio0-bus1 { 2262 rockchip,pins = 2263 <2 RK_PC4 1 &pcfg_pull_up>; 2264 }; 2265 2266 sdio0_bus4: sdio0-bus4 { 2267 rockchip,pins = 2268 <2 RK_PC4 1 &pcfg_pull_up>, 2269 <2 RK_PC5 1 &pcfg_pull_up>, 2270 <2 RK_PC6 1 &pcfg_pull_up>, 2271 <2 RK_PC7 1 &pcfg_pull_up>; 2272 }; 2273 2274 sdio0_cmd: sdio0-cmd { 2275 rockchip,pins = 2276 <2 RK_PD0 1 &pcfg_pull_up>; 2277 }; 2278 2279 sdio0_clk: sdio0-clk { 2280 rockchip,pins = 2281 <2 RK_PD1 1 &pcfg_pull_none>; 2282 }; 2283 2284 sdio0_cd: sdio0-cd { 2285 rockchip,pins = 2286 <2 RK_PD2 1 &pcfg_pull_up>; 2287 }; 2288 2289 sdio0_pwr: sdio0-pwr { 2290 rockchip,pins = 2291 <2 RK_PD3 1 &pcfg_pull_up>; 2292 }; 2293 2294 sdio0_bkpwr: sdio0-bkpwr { 2295 rockchip,pins = 2296 <2 RK_PD4 1 &pcfg_pull_up>; 2297 }; 2298 2299 sdio0_wp: sdio0-wp { 2300 rockchip,pins = 2301 <0 RK_PA3 1 &pcfg_pull_up>; 2302 }; 2303 2304 sdio0_int: sdio0-int { 2305 rockchip,pins = 2306 <0 RK_PA4 1 &pcfg_pull_up>; 2307 }; 2308 }; 2309 2310 sdmmc { 2311 sdmmc_bus1: sdmmc-bus1 { 2312 rockchip,pins = 2313 <4 RK_PB0 1 &pcfg_pull_up>; 2314 }; 2315 2316 sdmmc_bus4: sdmmc-bus4 { 2317 rockchip,pins = 2318 <4 RK_PB0 1 &pcfg_pull_up>, 2319 <4 RK_PB1 1 &pcfg_pull_up>, 2320 <4 RK_PB2 1 &pcfg_pull_up>, 2321 <4 RK_PB3 1 &pcfg_pull_up>; 2322 }; 2323 2324 sdmmc_clk: sdmmc-clk { 2325 rockchip,pins = 2326 <4 RK_PB4 1 &pcfg_pull_none>; 2327 }; 2328 2329 sdmmc_cmd: sdmmc-cmd { 2330 rockchip,pins = 2331 <4 RK_PB5 1 &pcfg_pull_up>; 2332 }; 2333 2334 sdmmc_cd: sdmmc-cd { 2335 rockchip,pins = 2336 <0 RK_PA7 1 &pcfg_pull_up>; 2337 }; 2338 2339 sdmmc_wp: sdmmc-wp { 2340 rockchip,pins = 2341 <0 RK_PB0 1 &pcfg_pull_up>; 2342 }; 2343 }; 2344 2345 suspend { 2346 ap_pwroff: ap-pwroff { 2347 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2348 }; 2349 2350 ddrio_pwroff: ddrio-pwroff { 2351 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2352 }; 2353 }; 2354 2355 spdif { 2356 spdif_bus: spdif-bus { 2357 rockchip,pins = 2358 <4 RK_PC5 1 &pcfg_pull_none>; 2359 }; 2360 2361 spdif_bus_1: spdif-bus-1 { 2362 rockchip,pins = 2363 <3 RK_PC0 3 &pcfg_pull_none>; 2364 }; 2365 }; 2366 2367 spi0 { 2368 spi0_clk: spi0-clk { 2369 rockchip,pins = 2370 <3 RK_PA6 2 &pcfg_pull_up>; 2371 }; 2372 spi0_cs0: spi0-cs0 { 2373 rockchip,pins = 2374 <3 RK_PA7 2 &pcfg_pull_up>; 2375 }; 2376 spi0_cs1: spi0-cs1 { 2377 rockchip,pins = 2378 <3 RK_PB0 2 &pcfg_pull_up>; 2379 }; 2380 spi0_tx: spi0-tx { 2381 rockchip,pins = 2382 <3 RK_PA5 2 &pcfg_pull_up>; 2383 }; 2384 spi0_rx: spi0-rx { 2385 rockchip,pins = 2386 <3 RK_PA4 2 &pcfg_pull_up>; 2387 }; 2388 }; 2389 2390 spi1 { 2391 spi1_clk: spi1-clk { 2392 rockchip,pins = 2393 <1 RK_PB1 2 &pcfg_pull_up>; 2394 }; 2395 spi1_cs0: spi1-cs0 { 2396 rockchip,pins = 2397 <1 RK_PB2 2 &pcfg_pull_up>; 2398 }; 2399 spi1_rx: spi1-rx { 2400 rockchip,pins = 2401 <1 RK_PA7 2 &pcfg_pull_up>; 2402 }; 2403 spi1_tx: spi1-tx { 2404 rockchip,pins = 2405 <1 RK_PB0 2 &pcfg_pull_up>; 2406 }; 2407 }; 2408 2409 spi2 { 2410 spi2_clk: spi2-clk { 2411 rockchip,pins = 2412 <2 RK_PB3 1 &pcfg_pull_up>; 2413 }; 2414 spi2_cs0: spi2-cs0 { 2415 rockchip,pins = 2416 <2 RK_PB4 1 &pcfg_pull_up>; 2417 }; 2418 spi2_rx: spi2-rx { 2419 rockchip,pins = 2420 <2 RK_PB1 1 &pcfg_pull_up>; 2421 }; 2422 spi2_tx: spi2-tx { 2423 rockchip,pins = 2424 <2 RK_PB2 1 &pcfg_pull_up>; 2425 }; 2426 }; 2427 2428 spi3 { 2429 spi3_clk: spi3-clk { 2430 rockchip,pins = 2431 <1 RK_PC1 1 &pcfg_pull_up>; 2432 }; 2433 spi3_cs0: spi3-cs0 { 2434 rockchip,pins = 2435 <1 RK_PC2 1 &pcfg_pull_up>; 2436 }; 2437 spi3_rx: spi3-rx { 2438 rockchip,pins = 2439 <1 RK_PB7 1 &pcfg_pull_up>; 2440 }; 2441 spi3_tx: spi3-tx { 2442 rockchip,pins = 2443 <1 RK_PC0 1 &pcfg_pull_up>; 2444 }; 2445 }; 2446 2447 spi4 { 2448 spi4_clk: spi4-clk { 2449 rockchip,pins = 2450 <3 RK_PA2 2 &pcfg_pull_up>; 2451 }; 2452 spi4_cs0: spi4-cs0 { 2453 rockchip,pins = 2454 <3 RK_PA3 2 &pcfg_pull_up>; 2455 }; 2456 spi4_rx: spi4-rx { 2457 rockchip,pins = 2458 <3 RK_PA0 2 &pcfg_pull_up>; 2459 }; 2460 spi4_tx: spi4-tx { 2461 rockchip,pins = 2462 <3 RK_PA1 2 &pcfg_pull_up>; 2463 }; 2464 }; 2465 2466 spi5 { 2467 spi5_clk: spi5-clk { 2468 rockchip,pins = 2469 <2 RK_PC6 2 &pcfg_pull_up>; 2470 }; 2471 spi5_cs0: spi5-cs0 { 2472 rockchip,pins = 2473 <2 RK_PC7 2 &pcfg_pull_up>; 2474 }; 2475 spi5_rx: spi5-rx { 2476 rockchip,pins = 2477 <2 RK_PC4 2 &pcfg_pull_up>; 2478 }; 2479 spi5_tx: spi5-tx { 2480 rockchip,pins = 2481 <2 RK_PC5 2 &pcfg_pull_up>; 2482 }; 2483 }; 2484 2485 testclk { 2486 test_clkout0: test-clkout0 { 2487 rockchip,pins = 2488 <0 RK_PA0 1 &pcfg_pull_none>; 2489 }; 2490 2491 test_clkout1: test-clkout1 { 2492 rockchip,pins = 2493 <2 RK_PD1 2 &pcfg_pull_none>; 2494 }; 2495 2496 test_clkout2: test-clkout2 { 2497 rockchip,pins = 2498 <0 RK_PB0 3 &pcfg_pull_none>; 2499 }; 2500 }; 2501 2502 tsadc { 2503 otp_pin: otp-pin { 2504 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2505 }; 2506 2507 otp_out: otp-out { 2508 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2509 }; 2510 }; 2511 2512 uart0 { 2513 uart0_xfer: uart0-xfer { 2514 rockchip,pins = 2515 <2 RK_PC0 1 &pcfg_pull_up>, 2516 <2 RK_PC1 1 &pcfg_pull_none>; 2517 }; 2518 2519 uart0_cts: uart0-cts { 2520 rockchip,pins = 2521 <2 RK_PC2 1 &pcfg_pull_none>; 2522 }; 2523 2524 uart0_rts: uart0-rts { 2525 rockchip,pins = 2526 <2 RK_PC3 1 &pcfg_pull_none>; 2527 }; 2528 }; 2529 2530 uart1 { 2531 uart1_xfer: uart1-xfer { 2532 rockchip,pins = 2533 <3 RK_PB4 2 &pcfg_pull_up>, 2534 <3 RK_PB5 2 &pcfg_pull_none>; 2535 }; 2536 }; 2537 2538 uart2a { 2539 uart2a_xfer: uart2a-xfer { 2540 rockchip,pins = 2541 <4 RK_PB0 2 &pcfg_pull_up>, 2542 <4 RK_PB1 2 &pcfg_pull_none>; 2543 }; 2544 }; 2545 2546 uart2b { 2547 uart2b_xfer: uart2b-xfer { 2548 rockchip,pins = 2549 <4 RK_PC0 2 &pcfg_pull_up>, 2550 <4 RK_PC1 2 &pcfg_pull_none>; 2551 }; 2552 }; 2553 2554 uart2c { 2555 uart2c_xfer: uart2c-xfer { 2556 rockchip,pins = 2557 <4 RK_PC3 1 &pcfg_pull_up>, 2558 <4 RK_PC4 1 &pcfg_pull_none>; 2559 }; 2560 }; 2561 2562 uart3 { 2563 uart3_xfer: uart3-xfer { 2564 rockchip,pins = 2565 <3 RK_PB6 2 &pcfg_pull_up>, 2566 <3 RK_PB7 2 &pcfg_pull_none>; 2567 }; 2568 2569 uart3_cts: uart3-cts { 2570 rockchip,pins = 2571 <3 RK_PC0 2 &pcfg_pull_none>; 2572 }; 2573 2574 uart3_rts: uart3-rts { 2575 rockchip,pins = 2576 <3 RK_PC1 2 &pcfg_pull_none>; 2577 }; 2578 }; 2579 2580 uart4 { 2581 uart4_xfer: uart4-xfer { 2582 rockchip,pins = 2583 <1 RK_PA7 1 &pcfg_pull_up>, 2584 <1 RK_PB0 1 &pcfg_pull_none>; 2585 }; 2586 }; 2587 2588 uarthdcp { 2589 uarthdcp_xfer: uarthdcp-xfer { 2590 rockchip,pins = 2591 <4 RK_PC5 2 &pcfg_pull_up>, 2592 <4 RK_PC6 2 &pcfg_pull_none>; 2593 }; 2594 }; 2595 2596 pwm0 { 2597 pwm0_pin: pwm0-pin { 2598 rockchip,pins = 2599 <4 RK_PC2 1 &pcfg_pull_none>; 2600 }; 2601 2602 pwm0_pin_pull_down: pwm0-pin-pull-down { 2603 rockchip,pins = 2604 <4 RK_PC2 1 &pcfg_pull_down>; 2605 }; 2606 2607 vop0_pwm_pin: vop0-pwm-pin { 2608 rockchip,pins = 2609 <4 RK_PC2 2 &pcfg_pull_none>; 2610 }; 2611 2612 vop1_pwm_pin: vop1-pwm-pin { 2613 rockchip,pins = 2614 <4 RK_PC2 3 &pcfg_pull_none>; 2615 }; 2616 }; 2617 2618 pwm1 { 2619 pwm1_pin: pwm1-pin { 2620 rockchip,pins = 2621 <4 RK_PC6 1 &pcfg_pull_none>; 2622 }; 2623 2624 pwm1_pin_pull_down: pwm1-pin-pull-down { 2625 rockchip,pins = 2626 <4 RK_PC6 1 &pcfg_pull_down>; 2627 }; 2628 }; 2629 2630 pwm2 { 2631 pwm2_pin: pwm2-pin { 2632 rockchip,pins = 2633 <1 RK_PC3 1 &pcfg_pull_none>; 2634 }; 2635 2636 pwm2_pin_pull_down: pwm2-pin-pull-down { 2637 rockchip,pins = 2638 <1 RK_PC3 1 &pcfg_pull_down>; 2639 }; 2640 }; 2641 2642 pwm3a { 2643 pwm3a_pin: pwm3a-pin { 2644 rockchip,pins = 2645 <0 RK_PA6 1 &pcfg_pull_none>; 2646 }; 2647 }; 2648 2649 pwm3b { 2650 pwm3b_pin: pwm3b-pin { 2651 rockchip,pins = 2652 <1 RK_PB6 1 &pcfg_pull_none>; 2653 }; 2654 }; 2655 2656 hdmi { 2657 hdmi_i2c_xfer: hdmi-i2c-xfer { 2658 rockchip,pins = 2659 <4 RK_PC1 3 &pcfg_pull_none>, 2660 <4 RK_PC0 3 &pcfg_pull_none>; 2661 }; 2662 2663 hdmi_cec: hdmi-cec { 2664 rockchip,pins = 2665 <4 RK_PC7 1 &pcfg_pull_none>; 2666 }; 2667 }; 2668 2669 pcie { 2670 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2671 rockchip,pins = 2672 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2673 }; 2674 2675 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2676 rockchip,pins = 2677 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2678 }; 2679 }; 2680 2681 }; 2682}; 2683