| /arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/ |
| D | reg_alloc_stat.cpp | 22 std::vector<bool> used_regs(INVALID_REG); in RegAllocStat()
23 std::vector<bool> used_vregs(INVALID_REG); in RegAllocStat()
24 std::vector<bool> used_slots(INVALID_REG); in RegAllocStat()
25 std::vector<bool> used_vslots(INVALID_REG); in RegAllocStat()
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| D | interference_graph.h | 115 Register color_ = INVALID_REG;
216 Register color = INVALID_REG;
227 if (node.GetColor() != INVALID_REG) { in UpdateBiasData()
261 if (node.GetColor() != INVALID_REG) { in AssignColors()
270 if (node.HasBias() && biases_[node.GetBias()].color != INVALID_REG && in AssignColors()
292 if (node.HasBias() && biases_[node.GetBias()].color == INVALID_REG) { in AssignColors()
319 if (nbr_node.GetColor() != INVALID_REG && HasEdge(id, nbr_id)) { in MakeBusyBitmap()
325 if (biases_[nbr_node.GetBias()].color != INVALID_REG) { in MakeBusyBitmap()
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| D | interference_graph.cpp | 200 colors.fill(INVALID_REG); in Dump()
204 if (!(skip_physical && node.IsPhysical()) && colors[node.GetColor()] == INVALID_REG) { in Dump()
225 GetNode(node_num).GetColor() != INVALID_REG) { in Dump()
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| D | reg_alloc_base.cpp | 170 if (inst->GetDstReg() != INVALID_REG) { in SetPreassignedRegisters()
194 interval->SetPreassignedReg(INVALID_REG); in SetPreassignedRegisters()
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| D | reg_alloc_graph_coloring.cpp | 276 ASSERT(color != INVALID_REG); in Remap()
350 if (interval->IsPreassigned() && interval->GetReg() == INVALID_REG) { in InitWorkingRanges()
351 ASSERT(interval->GetReg() != INVALID_REG); in InitWorkingRanges()
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| D | spill_fills_resolver.cpp | 22 : SpillFillsResolver(graph, INVALID_REG, MAX_NUM_REGS, MAX_NUM_VREGS) in SpillFillsResolver()
318 if (resolver_ != INVALID_REG) { in GetResolver()
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| D | reg_alloc_resolver.cpp | 233 inst->SetDstReg(INVALID_REG); in ResolveOutput()
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| /arkcompiler/runtime_core/compiler/optimizer/ir/ |
| D | locations.h | 132 return GetValue() != INVALID_REG; in IsRegisterValid()
155 return IsAnyRegister() && GetValue() == INVALID_REG; in IsUnallocatedRegister()
160 return IsAnyRegister() && GetValue() != INVALID_REG; in IsFixedRegister()
210 return Location(Kind::REGISTER, INVALID_REG); in RequireRegister()
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| D | constants.h | 42 constexpr Register INVALID_REG = std::numeric_limits<Register>::max();
48 constexpr Register VIRTUAL_FRAME_SIZE = INVALID_REG - 1U;
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| D | ir_constructor.h | 123 inst->SetSrcReg(i, INVALID_REG); in NewInst()
1136 if (inst->GetDstReg() != INVALID_REG && !inst->IsOperandsDynamic()) { in PropagateRegisters()
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| D | dump.cpp | 435 if (spill_fill.DstValue() != INVALID_REG) { in Dump()
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| /arkcompiler/runtime_core/bytecode_optimizer/ |
| D | reg_acc_alloc.cpp | 183 compiler::Register reg = need ? compiler::INVALID_REG : compiler::ACC_REG_ID; in SetNeedLda()
208 inst->SetSrcReg(i, compiler::INVALID_REG); in RunImpl()
210 inst->SetDstReg(compiler::INVALID_REG); in RunImpl()
272 input->SetDstReg(compiler::INVALID_REG); in RunImpl()
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| D | reg_encoder.h | 76 RegContent() : reg(compiler::INVALID_REG), type(compiler::DataType::NO_TYPE) {} in RegContent()
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| D | codegen.cpp | 247 ASSERT(sf.SrcValue() != compiler::INVALID_REG && sf.DstValue() != compiler::INVALID_REG); in EncodeSpillFillData()
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| D | reg_encoder.cpp | 146 return r != panda::compiler::ACC_REG_ID && r != panda::compiler::INVALID_REG; in RegNeedsRenumbering()
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| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/ |
| D | extend_assembler.h | 90 if (ret.GetId() == INVALID_REG) { in CallDispatcherArgument()
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| D | assembler_aarch64.h | 59 return reg_ != RegisterId::INVALID_REG; in IsValid()
160 : reg_(RegisterId::INVALID_REG), extend_(Extend::NO_EXTEND), shift_(Shift::NO_SHIFT), in Operand()
239 : base_(base), offsetReg_(RegisterId::INVALID_REG), offsetImm_(offset), addrmod_(addrmod), in base_()
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| D | assembler_aarch64_constants.h | 26 INVALID_REG = 0xFF, enumerator
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| /arkcompiler/runtime_core/compiler/tests/ |
| D | reg_alloc_common_test.cpp | 186 EXPECT_NE(inst->GetDstReg(), INVALID_REG); in TEST_F()
229 EXPECT_NE(reg, INVALID_REG); in TEST_F()
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| D | life_intervals_test.cpp | 217 if (graph->GetZeroReg() == INVALID_REG) { in TEST_F()
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| D | compiler_regalloc_test.cpp | 162 bias.color = INVALID_REG; in __anon5d7559aa0502()
519 Register color = INVALID_REG; in __anon5d7559aa0d02()
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| /arkcompiler/runtime_core/bytecode_optimizer/tests/ |
| D | codegen_test.cpp | 192 Register reg = INVALID_REG; in __anon0774c0120302()
305 Register reg2 = INVALID_REG; in __anon0774c0120502()
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| /arkcompiler/ets_runtime/ecmascript/compiler/trampoline/aarch64/ |
| D | common_call.h | 197 Register acc = INVALID_REG);
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| D | asm_interpreter_call.cpp | 344 return INVALID_REG; in GetThisRegsiter()
365 return INVALID_REG; in GetNewTargetRegsiter()
1084 if (accRegister == INVALID_REG) { in DispatchCall()
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| /arkcompiler/runtime_core/compiler/optimizer/ir_builder/ |
| D | inst_builder.cpp | 33 ASSERT(!GetGraph()->IsBytecodeOptimizer() || reg_num != INVALID_REG); in Prepare()
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