1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef HDMI_FRL_H 10 #define HDMI_FRL_H 11 12 #include "hdf_base.h" 13 #include "osal_time.h" 14 15 #ifdef __cplusplus 16 #if __cplusplus 17 extern "C" { 18 #endif 19 #endif /* __cplusplus */ 20 21 /* FRL(Fix Rate Link) */ 22 enum HdmiFrlMode { 23 HDMI_FRL_MODE_TMDS = 0, 24 HDMI_FRL_MODE_FRL = 1, 25 HDMI_FRL_MODE_BUTT, 26 }; 27 28 #define HDMI_FRL_3_LANES 3 29 #define HDMI_FRL_4_LANES 4 30 31 enum HdmiFrlWorkMode { 32 HDMI_FRL_WORK_MODE_NONE = 0, 33 HDMI_FRL_WORK_MODE_3L3G = 1, /* 3 lanes, 3Gbps per lane */ 34 HDMI_FRL_WORK_MODE_3L6G = 2, /* 3 lanes, 6Gbps per lane */ 35 HDMI_FRL_WORK_MODE_4L6G = 3, /* 4 lanes, 6Gbps per lane */ 36 HDMI_FRL_WORK_MODE_4L8G = 4, /* 4 lanes, 8Gbps per lane */ 37 HDMI_FRL_WORK_MODE_4L10G = 5, /* 4 lanes, 10Gbps per lane */ 38 HDMI_FRL_WORK_MODE_4L12G = 6, /* 4 lanes, 12Gbps per lane */ 39 HDMI_FRL_WORK_MODE_BUTT, 40 }; 41 42 enum HdmiFrlBitRate { 43 HDMI_FRL_BIT_RATE_3 = 3, 44 HDMI_FRL_BIT_RATE_6 = 6, 45 HDMI_FRL_BIT_RATE_8 = 8, 46 HDMI_FRL_BIT_RATE_10 = 10, 47 HDMI_FRL_BIT_RATE_12 = 12, 48 HDMI_FRL_BIT_RATE_BUTT, 49 }; 50 51 enum HdmiFrlTrainPattern { 52 HDMI_FRL_TRAIN_PATTERN_NULL = 0, 53 HDMI_FRL_TRAIN_PATTERN_LP1 = 1, 54 HDMI_FRL_TRAIN_PATTERN_LP2 = 2, 55 HDMI_FRL_TRAIN_PATTERN_LP3 = 3, 56 HDMI_FRL_TRAIN_PATTERN_LP4 = 4, 57 HDMI_FRL_TRAIN_PATTERN_LP5 = 5, 58 HDMI_FRL_TRAIN_PATTERN_LP6 = 6, 59 HDMI_FRL_TRAIN_PATTERN_LP7 = 7, 60 HDMI_FRL_TRAIN_PATTERN_LP8 = 8, 61 HDMI_FRL_TRAIN_PATTERN_REV = 9, 62 HDMI_FRL_TRAIN_PATTERN_0E = 14, 63 HDMI_FRL_TRAIN_PATTERN_0F = 15, 64 HDMI_FRL_TRAIN_PATTERN_BUTT, 65 }; 66 67 enum HdmiFrlTrainStatus { 68 HDMI_FRL_TRAIN_STATUS_NULL = 0, 69 HDMI_FRL_TRAIN_STATUS_FAIL = 1, 70 HDMI_FRL_TRAIN_STATUS_SUCC = 2, 71 HDMI_FRL_TRAIN_STATUS_BUSY = 3, 72 HDMI_FRL_TRAIN_STATUS_BUTT, 73 }; 74 75 enum HdmiFrlTrainingFailReason { 76 HDMI_FRL_TRAIN_FAIL_NORMAL, 77 HDMI_FRL_TRAIN_FAIL_FLT_TIMEOUT, 78 HDMI_FRL_TRAIN_FAIL_FLT_STEP_TIMEOUT, 79 HDMI_FRL_TRAIN_FAIL_RATE_CHANGE, 80 HDMI_FRL_TRAIN_FAIL_FFE_CHANGE, 81 HDMI_FRL_TRAIN_FAIL_BUTT 82 }; 83 84 enum HdmiFrlTrainStep { 85 HDMI_FRL_TRAIN_STEP_READR_CHECK = 0, 86 HDMI_FRL_TRAIN_STEP_TRAIN_START = 1, 87 HDMI_FRL_TRAIN_STEP_RESULT_CHECK = 2, 88 HDMI_FRL_TRAIN_STEP_RATE_CHANGE = 3, 89 HDMI_FRL_TRAIN_STEP_RESULT_HANDLE = 4, 90 HDMI_FRL_TRAIN_STEP_RETRAIN_CHECK = 5, 91 HDMI_FRL_TRAIN_STEP_TRAIN_STOP = 6, 92 HDMI_FRL_TRAIN_STEP_BUTT, 93 }; 94 95 enum HdmiFrlRateSelect { 96 HDMI_FRL_RATE_LITTLE = 0, 97 HDMI_FRL_RATE_BIG = 1, 98 HDMI_FRL_RATE_BUTT, 99 }; 100 101 enum HdmiFrlPixelFormatMode { 102 HDMI_FRL_PIXEL_FORMAT_MODE_0 = 0, 103 HDMI_FRL_PIXEL_FORMAT_MODE_1 = 1, 104 HDMI_FRL_PIXEL_FORMAT_MODE_2 = 2, 105 HDMI_FRL_PIXEL_FORMAT_MODE_3 = 3, 106 }; 107 108 enum HdmiFrlBypass { 109 HDMI_FRL_BYPASS_READ_CHECK = 0x01, 110 HDMI_FRL_BYPASS_RESULT_CHECK = 0x02, 111 HDMI_FRL_BYPASS_RETRAIN_CHECK = 0x04, 112 }; 113 114 /* 115 * Feed Forward Equalizer(FFE) 116 * Tx terminal will use 0=TxFFE0 FFE in Link Training. If higher rate signal needs to be transmitted, 117 * Tx will decide higher FFE compensation through Link Training to ensure 118 * that video and audio data can be completely transmitted to the Sink terminal. 119 */ 120 enum HdmiFrlTxffeMode { 121 HDMI_FRL_TXFFE_MODE_0 = 0, 122 HDMI_FRL_TXFFE_MODE_1 = 1, 123 HDMI_FRL_TXFFE_MODE_2 = 2, 124 HDMI_FRL_TXFFE_MODE_3 = 3, 125 HDMI_FRL_TXFFE_MODE_BUTT, 126 }; 127 128 enum HdmiFrlStrategyMode { 129 HDMI_FRL_STRATEGY_MODE_1, 130 HDMI_FRL_STRATEGY_MODE_2, 131 HDMI_FRL_STRATEGY_MODE_3, 132 HDMI_FRL_STRATEGY_MODE_BUTT 133 }; 134 135 enum HdmiFrlStateMachineRunningState { 136 HDMI_FRL_STATE_MACHINE_NULL = 0, 137 HDMI_FRL_STATE_MACHINE_START = 1, 138 HDMI_FRL_STATE_MACHINE_STOP = 2, 139 }; 140 141 struct HdmiFrlStateMachineInfo { 142 bool start; 143 enum HdmiFrlTrainStep trainingState; 144 enum HdmiFrlStateMachineRunningState machineState; 145 uint64_t startTime; /* ms */ 146 uint32_t waitReadyTime; /* ms */ 147 uint32_t waitHandleTime; /* ms */ 148 uint32_t waitRetrainTime; /* ms */ 149 uint32_t trainTimeout; /* ms */ 150 uint32_t timeoutCnt; 151 }; 152 153 struct HdmiFrlInfo { 154 uint8_t curFrlRate; 155 uint8_t minFrlRate; 156 uint8_t maxFrlRate; 157 uint8_t preFrlRate; 158 uint32_t trainFailCnt; 159 uint32_t trainMaxFailTimes; 160 uint32_t tmdsClock; 161 enum HdmiFrlMode perMode; 162 enum HdmiFrlMode mode; 163 enum HdmiFrlStrategyMode strategy; 164 enum HdmiFrlRateSelect rateSelect; 165 bool scdc; 166 bool ctsMode; 167 bool start; 168 bool work; 169 struct HdmiFrlStateMachineInfo machineInfo; 170 uint32_t trainingFailCnt; 171 uint32_t trainingMaxFailTimes; 172 }; 173 174 struct HdmiFrl { 175 struct HdmiFrlInfo info; 176 void *priv; 177 }; 178 179 struct HdmiFrlAudioNctsConfig { 180 enum HdmiSampleRate sampleRate; 181 enum HdmiFrlMode mode; 182 uint8_t frlRate; 183 uint32_t pixelClk; 184 uint32_t n; 185 uint32_t cts; 186 }; 187 188 struct HdmiFrlTrainConfig { 189 bool frlNoTimeout; 190 uint8_t frlRate; 191 uint8_t txffe; 192 uint32_t trainTimeout; 193 }; 194 195 struct HdmiFrlTrainRslt { 196 enum HdmiFrlTrainStatus status; 197 enum HdmiFrlTrainPattern pattern[HDMI_FRL_4_LANES]; 198 enum HdmiFrlTrainingFailReason failReason; 199 }; 200 201 void HdmiFrlEnable(struct HdmiFrl *frl, bool enable); 202 bool HdmiFrlSupport(struct HdmiFrl *frl); 203 int32_t HdmiFrlModeSelect(struct HdmiFrl *frl); 204 bool HdmiFrlModeChanged(struct HdmiFrl *frl); 205 void HdmiFrlTrainingStateMachineHandle(struct HdmiFrl *frl); 206 void HdmiFrlTrainingStateMachineTimeoutHandle(struct HdmiFrl *frl); 207 208 #ifdef __cplusplus 209 #if __cplusplus 210 } 211 #endif 212 #endif /* __cplusplus */ 213 214 #endif /* HDMI_FRL_H */ 215