Searched refs:AT91_PMC_PLLADIV2 (Results 1 – 2 of 2) sorted by relevance
30 if (mckr & AT91_PMC_PLLADIV2) in clk_plldiv_recalc_rate()61 regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2, in clk_plldiv_set_rate()62 parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); in clk_plldiv_set_rate()
135 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ macro