Searched refs:B5_XS_CSR (Results 1 – 2 of 2) sorted by relevance
214 #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ macro
800 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ; in fddi_isr()814 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ; in fddi_isr()