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Searched refs:BIT6 (Results 1 – 25 of 50) sorted by relevance

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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h57 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL co…
64 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 int…
75 …{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
163 …{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
212 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW in…
Dhal_com_reg.h562 #define HSIMR_RON_INT_EN BIT6
571 #define HSISR_RON_INT BIT6
614 #define RRSR_12M BIT6
798 #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */
846 #define PHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */
897 #define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */
951 #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */
1009 #define StopBecon BIT6
1045 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */
1573 #define SDIO_HIMR_TXBCNOK_MSK BIT6
[all …]
Drtl8723b_spec.h220 #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */
Dosdep_service.h27 #define BIT6 0x00000040 macro
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h222 #define IMR_MGNTDOK BIT6
237 #define TPPoll_MQ BIT6
277 #define AcmHw_VoqStatus BIT6
367 #define RRSR_12M BIT6
/kernel/linux/linux-5.10/drivers/video/fbdev/via/
Dlcd.c376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
611 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
620 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
633 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
639 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
663 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
688 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
694 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
Ddvi.c55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
421 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
Dhw.c1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1680 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2033 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2035 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2041 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2043 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
/kernel/linux/linux-5.10/drivers/scsi/
Ddc395x.h70 #define BIT6 0x00000040 macro
138 #define DATAIN BIT6
180 #define EN_ATN_STOP BIT6
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h37 #define BIT6 0x00000040 macro
Dhalbtc8821a2ant.h9 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
Dhalbtc8821a1ant.h9 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
Dhalbtc8192e2ant.h8 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
Dhalbtc8723b2ant.h11 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
444 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
642 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
/kernel/linux/linux-5.10/drivers/char/pcmcia/
Dsynclink_cs.c299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
679 #define CMD_RXRESET BIT6 // receiver reset
927 if (status & (BIT7 + BIT6)) { in rx_ready_async()
941 else if (status & BIT6) in rx_ready_async()
1476 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1478 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2184 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2186 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
[all …]
/kernel/linux/linux-5.10/drivers/net/hamradio/
Dz8530.h118 #define BIT6 1 /* 6 bit/8bit sync */ macro
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
Dodm_debug.h67 #define ODM_COMP_ANT_DIV BIT6
Dodm.h425 ODM_BB_ANT_DIV = BIT6,
488 ODM_RF_RX_C = BIT6,
534 ODM_AD_HOC = BIT6,
548 ODM_WM_AC = BIT6,
DHalHWImg8723B_MAC.c19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
DHalBtc8723b2Ant.h9 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
/kernel/linux/linux-5.10/drivers/tty/serial/
Dzs.h173 #define BIT6 1 /* 6 bit/8bit sync */ macro
Dsunzilog.h156 #define BIT6 1 /* 6 bit/8bit sync */ macro
Dip22zilog.h154 #define BIT6 1 /* 6 bit/8bit sync */ macro
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/
Drtl819x_Qos.h16 #define BIT6 0x00000040 macro

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