| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/ |
| D | rtl8723b_spec.h | 217 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
246 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
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| D | hal_com_reg.h | 617 #define RRSR_36M BIT9
795 #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrup */
811 #define IMR_C2HCMD BIT9
843 #define PHIMR_CPWM2 BIT9
866 #define PHIMR_TXFOVW BIT9
894 #define UHIMR_CPWM2 BIT9
919 #define UHIMR_TXFOVW BIT9
948 #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
977 #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */
1042 #define RCR_AICV BIT9 /* Accept ICV error packet */
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| D | osdep_service.h | 30 #define BIT9 0x00000200 macro
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| D | rtw_mlme_ext.h | 53 #define DYNAMIC_BB_RATE_ADAPTIVE BIT9 /* ODM_BB_RATE_ADAPTIVE */
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| /kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 219 #define IMR_BDOK BIT9
240 #define TPPoll_StopBK BIT9
370 #define RRSR_36M BIT9
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 40 #define BIT9 0x00000200 macro
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| D | halbtcoutsrc.h | 101 #define ALGO_TRACE_SW_EXEC BIT9
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| D | halbtc8192e2ant.c | 2631 u16tmp |= BIT9; in btc8192e2ant_init_hwconfig()
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| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/ |
| D | Hal8723BReg.h | 399 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
428 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
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| D | odm_RegDefine11N.h | 160 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
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| D | odm_debug.h | 70 #define ODM_COMP_RATE_ADAPTIVE BIT9
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| D | HalBtcOutSrc.h | 102 #define ALGO_TRACE_SW_EXEC BIT9
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| D | odm.h | 428 ODM_BB_RATE_ADAPTIVE = BIT9,
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| D | odm_DIG.c | 24 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
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| /kernel/linux/linux-5.10/drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 19 #define BIT9 0x00000200 macro
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| /kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/ |
| D | synclink.h | 32 #define BIT9 0x0200 macro
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| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | synclink.h | 28 #define BIT9 0x0200 macro
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| /kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/ |
| D | synclink.h | 19 #define BIT9 0x0200 macro
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| /kernel/linux/linux-5.10/drivers/scsi/ |
| D | dc395x.h | 67 #define BIT9 0x00000200 macro
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| /kernel/linux/linux-5.10/drivers/tty/ |
| D | synclink.c | 562 #define MISCSTATUS_DSR_LATCHED BIT9
585 #define SICR_DSR_ACTIVE BIT9
587 #define SICR_DSR (BIT9|BIT8)
1595 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()
1704 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()
4603 RegValue |= BIT9; in usc_set_sdlc_mode()
4605 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4675 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4677 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4840 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
[all …]
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| D | synclink_gt.c | 390 #define IRQ_RXIDLE BIT9 /* HDLC */
391 #define IRQ_RXBREAK BIT9 /* async */
4071 val |= BIT9; in async_mode()
4111 val |= BIT9; in async_mode()
4234 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4235 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4307 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4308 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4951 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| D | reg.h | 367 #define RRSR_36M BIT9
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| /kernel/linux/linux-5.10/drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 723 #define LPFC_SLI4_INTR9 BIT9
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| /kernel/linux/linux-5.10/drivers/char/pcmcia/ |
| D | synclink_cs.c | 296 #define IRQ_TXREPEAT BIT9 // tx message repeat
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