Home
last modified time | relevance | path

Searched refs:CLK_DIVIDER_HIWORD_MASK (Results 1 – 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dclk-hi3660.c336 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
338 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
340 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
342 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
344 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
346 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
348 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
350 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
352 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
354 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
Dclk-hi3670.c488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
Dclk-hi3620.c124 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
125 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
126 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
127 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
128 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
129 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
130 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
/kernel/linux/linux-5.10/drivers/clk/
Dclk-divider.c436 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_divider_set_rate()
478 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { in __clk_hw_register_divider()
/kernel/linux/linux-5.10/drivers/clk/rockchip/
Dclk-half-divider.c125 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_half_divider_set_rate()
Dclk-rk3036.c144 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3128.c169 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3228.c179 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3328.c232 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3188.c236 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rv1108.c162 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3368.c152 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3288.c245 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-px30.c204 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3308.c194 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
Dclk-rk3399.c241 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
/kernel/linux/linux-5.10/include/linux/
Dclk-provider.h612 #define CLK_DIVIDER_HIWORD_MASK BIT(3) macro