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Searched refs:CLK_PLL (Results 1 – 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr7s9210-cpg-mssr.c51 CLK_PLL, enumerator
63 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
66 DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
77 DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
78 DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
79 DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
80 DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
81 DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
177 case CLK_PLL: in rza2_cpg_clk_register()
/kernel/linux/linux-5.10/arch/c6x/platforms/
Dplldata.c41 .flags = CLK_PLL,
46 .flags = CLK_PLL,
51 .flags = CLK_PLL,
56 .flags = CLK_PLL,
61 .flags = CLK_PLL,
66 .flags = CLK_PLL,
71 .flags = CLK_PLL,
76 .flags = CLK_PLL,
81 .flags = CLK_PLL,
86 .flags = CLK_PLL,
[all …]
Dpll.c335 else if (clk->flags & CLK_PLL) in __init_clk()
382 if (parent->flags & CLK_PLL) in dump_clock()
/kernel/linux/linux-5.10/drivers/clk/
Dclk-bm1880.c174 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ macro
206 CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
208 CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
210 CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
212 CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
/kernel/linux/linux-5.10/arch/c6x/include/asm/
Dclock.h98 #define CLK_PLL BIT(2) /* PLL-derived clock */ macro
/kernel/linux/linux-5.10/drivers/media/usb/stkwebcam/
Dstk-sensor.c99 #define CLK_PLL 0x80 /* Enable internal PLL */ macro
301 {REG_CLKRC, CLK_PLL},