Searched refs:DCE3_HDMI_OFFSET0 (Results 1 – 3 of 3) sorted by relevance
198 #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400) macro
3648 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()3649 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_disable_interrupt_state()3794 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()3890 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); in r600_irq_set()3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()4002 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); in r600_irq_ack()4004 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_irq_ack()
1550 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; in radeon_afmt_init()